mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 21:32:10 +00:00
7fdf962e5c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
968 B
TableGen
23 lines
968 B
TableGen
//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines the itinerary class data for the ARM v6 processors.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def V6Itineraries : ProcessorItineraries<[
|
|
InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
|
|
InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
|
|
InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
|
|
InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
|
|
InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
|
|
InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
|
|
InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
|
|
]>;
|