mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-15 11:57:30 +00:00
700ed80d3d
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
3.9 KiB
C++
153 lines
3.9 KiB
C++
//===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "nvptx-reg-info"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTX.h"
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#include "NVPTXSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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namespace llvm
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{
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std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
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if (RC == &NVPTX::Float32RegsRegClass) {
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return ".f32";
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}
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if (RC == &NVPTX::Float64RegsRegClass) {
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return ".f64";
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}
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else if (RC == &NVPTX::Int64RegsRegClass) {
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return ".s64";
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}
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else if (RC == &NVPTX::Int32RegsRegClass) {
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return ".s32";
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}
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else if (RC == &NVPTX::Int16RegsRegClass) {
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return ".s16";
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}
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// Int8Regs become 16-bit registers in PTX
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else if (RC == &NVPTX::Int8RegsRegClass) {
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return ".s16";
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}
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else if (RC == &NVPTX::Int1RegsRegClass) {
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return ".pred";
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}
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else if (RC == &NVPTX::SpecialRegsRegClass) {
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return "!Special!";
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}
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else {
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return "INTERNAL";
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}
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return "";
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}
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std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
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if (RC == &NVPTX::Float32RegsRegClass) {
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return "%f";
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}
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if (RC == &NVPTX::Float64RegsRegClass) {
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return "%fd";
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}
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else if (RC == &NVPTX::Int64RegsRegClass) {
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return "%rd";
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}
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else if (RC == &NVPTX::Int32RegsRegClass) {
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return "%r";
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}
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else if (RC == &NVPTX::Int16RegsRegClass) {
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return "%rs";
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}
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else if (RC == &NVPTX::Int8RegsRegClass) {
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return "%rc";
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}
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else if (RC == &NVPTX::Int1RegsRegClass) {
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return "%p";
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}
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else if (RC == &NVPTX::SpecialRegsRegClass) {
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return "!Special!";
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}
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else {
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return "INTERNAL";
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}
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return "";
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}
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}
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NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
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const NVPTXSubtarget &st)
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: NVPTXGenRegisterInfo(0),
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Is64Bit(st.is64Bit()) {}
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#define GET_REGINFO_TARGET_DESC
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#include "NVPTXGenRegisterInfo.inc"
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/// NVPTX Callee Saved Registers
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const uint16_t* NVPTXRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const {
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static const uint16_t CalleeSavedRegs[] = { 0 };
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return CalleeSavedRegs;
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}
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// NVPTX Callee Saved Reg Classes
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const TargetRegisterClass* const*
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NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
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return CalleeSavedRegClasses;
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}
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BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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return Reserved;
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}
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void NVPTXRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum+1).getImm();
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// Using I0 as the frame pointer
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MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
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MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
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}
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int NVPTXRegisterInfo::
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getDwarfRegNum(unsigned RegNum, bool isEH) const {
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return 0;
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}
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unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return NVPTX::VRFrame;
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}
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unsigned NVPTXRegisterInfo::getRARegister() const {
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return 0;
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}
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