mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 17:07:06 +00:00
91c5346d91
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar: 11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
906 lines
42 KiB
C++
906 lines
42 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instruction set to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class InstrItineraryData;
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class LiveVariables;
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class MCAsmInfo;
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class MachineMemOperand;
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class MachineRegisterInfo;
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class MDNode;
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class MCInst;
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class SDNode;
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class ScheduleHazardRecognizer;
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class SelectionDAG;
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class ScheduleDAG;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class BranchProbability;
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template<class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instruction set
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///
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class TargetInstrInfo : public MCInstrInfo {
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
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: CallFrameSetupOpcode(CFSetupOpcode),
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CallFrameDestroyOpcode(CFDestroyOpcode) {
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}
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virtual ~TargetInstrInfo();
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/// getRegClass - Givem a machine instruction descriptor, returns the register
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/// class constraint for OpNum, or NULL.
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const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
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unsigned OpNum,
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const TargetRegisterInfo *TRI,
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const MachineFunction &MF) const;
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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bool isTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA = 0) const {
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return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
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(MI->getDesc().isRematerializable() &&
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(isReallyTriviallyReMaterializable(MI, AA) ||
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isReallyTriviallyReMaterializableGeneric(MI, AA)));
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}
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protected:
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/// isReallyTriviallyReMaterializable - For instructions with opcodes for
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/// which the M_REMATERIALIZABLE flag is set, this hook lets the target
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/// specify whether the instruction is actually trivially rematerializable,
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/// taking into consideration its operands. This predicate must return false
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/// if the instruction has any side effects other than producing a value, or
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/// if it requres any address registers that are not always available.
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virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const {
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return false;
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}
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private:
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/// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
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/// for which the M_REMATERIALIZABLE flag is set and the target hook
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/// isReallyTriviallyReMaterializable returns false, this function does
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/// target-independent tests to determine if the instruction is really
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/// trivially rematerializable.
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bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
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AliasAnalysis *AA) const;
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public:
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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/// between operating with a frame pointer and operating without, through the
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/// use of these two instructions.
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///
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// hasLoadFromStackSlot - If the specified machine instruction has
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/// a load from a stack slot, return true along with the FrameIndex
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/// of the loaded stack slot and the machine mem operand containing
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/// the reference. If not, return false. Unlike
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/// isLoadFromStackSlot, this returns true for any instructions that
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/// loads from the stack. This is just a hint, as some cases may be
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/// missed.
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virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// hasStoreToStackSlot - If the specified machine instruction has a
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/// store to a stack slot, return true along with the FrameIndex of
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/// the loaded stack slot and the machine mem operand containing the
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/// reference. If not, return false. Unlike isStoreToStackSlot,
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/// this returns true for any instructions that stores to the
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/// stack. This is just a hint, as some cases may be missed.
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virtual bool hasStoreToStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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return 0;
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}
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/// reMaterialize - Re-issue the specified 'original' instruction at the
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/// specific location targeting a new destination register.
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/// The register in Orig->getOperand(0).getReg() will be substituted by
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/// DestReg:SubIdx. Any existing subreg index is preserved or composed with
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/// SubIdx.
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const = 0;
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/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
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/// two-addrss instruction inserted by two-address pass.
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virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
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MachineInstr *UseMI,
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const TargetRegisterInfo &TRI) const {
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// Do nothing.
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}
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/// duplicate - Create a duplicate of the Orig instruction in MF. This is like
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/// MachineFunction::CloneMachineInstr(), but the target may update operands
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/// that are required to be unique.
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///
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/// The instruction must be duplicable as indicated by isNotDuplicable().
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virtual MachineInstr *duplicate(MachineInstr *Orig,
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MachineFunction &MF) const = 0;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into one or more true
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/// three-address instructions on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the last new instruction.
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///
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
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return 0;
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}
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/// commuteInstruction - If a target has any instructions that are
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/// commutable but require converting to different instructions or making
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/// non-trivial changes to commute them, this method can overloaded to do
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/// that. The default implementation simply swaps the commutable operands.
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/// If NewMI is false, MI is modified in place and returned; otherwise, a
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/// new machine instruction is created and returned. Do not call this
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/// method for a non-commutable instruction, but there may be some cases
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/// where this method fails and returns null.
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const = 0;
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/// findCommutedOpIndices - If specified MI is commutable, return the two
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/// operand indices that would swap value. Return false if the instruction
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/// is not in a form which this routine understands.
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virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const = 0;
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/// produceSameValue - Return true if two machine instructions would produce
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/// identical values. By default, this is only true when the two instructions
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/// are deemed identical except for defs. If this function is called when the
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/// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
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/// aggressive checks.
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virtual bool produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI = 0) const = 0;
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with a conditional branch and it falls through to a
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/// successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These operands can be
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/// passed to other TargetInstrInfo methods to create new branches.
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/// 4. If this block ends with a conditional branch followed by an
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/// unconditional branch, it returns the 'true' destination in TBB, the
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/// 'false' destination in FBB, and a list of operands that evaluate the
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/// condition. These operands can be passed to other TargetInstrInfo
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/// methods to create new branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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///
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const {
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return true;
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}
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/// RemoveBranch - Remove the branching code at the end of the specific MBB.
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/// This is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
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}
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/// InsertBranch - Insert branch code into the end of the specified
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/// MachineBasicBlock. The operands to this method are the same as those
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/// returned by AnalyzeBranch. This is only invoked in cases where
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/// AnalyzeBranch returns success. It returns the number of instructions
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/// inserted.
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///
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/// It is also invoked by tail merging to add unconditional branches in
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/// cases where AnalyzeBranch doesn't apply because there was no original
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/// branch to analyze. At least this much must be implemented, else tail
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/// merging needs to be disabled.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
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}
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/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
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/// after it, replacing it with an unconditional branch to NewDest. This is
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/// used by the tail merging pass.
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virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const = 0;
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/// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
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/// block at the specified instruction (i.e. instruction would be the start
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/// of a new basic block).
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virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const {
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return true;
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}
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/// isProfitableToIfCvt - Return true if it's profitable to predicate
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/// instructions with accumulated instruction latency of "NumCycles"
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/// of the specified basic block, where the probability of the instructions
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/// being executed is given by Probability, and Confidence is a measure
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/// of our confidence that it will be properly predicted.
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virtual
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const {
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return false;
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}
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/// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
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/// checks for the case where two basic blocks from true and false path
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/// of a if-then-else (diamond) are predicated on mutally exclusive
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/// predicates, where the probability of the true path being taken is given
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/// by Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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virtual bool
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isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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const BranchProbability &Probability) const {
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return false;
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}
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/// isProfitableToDupForIfCvt - Return true if it's profitable for
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/// if-converter to duplicate instructions of specified accumulated
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/// instruction latencies in the specified MBB to enable if-conversion.
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/// The probability of the instructions being executed is given by
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/// Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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virtual bool
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isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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const BranchProbability &Probability) const {
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return false;
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}
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/// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
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/// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
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/// exclusive predicates.
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/// e.g.
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/// subeq r0, r1, #1
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/// addne r0, r1, #1
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/// =>
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/// sub r0, r1, #1
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/// addne r0, r1, #1
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///
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/// This may be profitable is conditional instructions are always executed.
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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/// copyPhysReg - Emit instructions to copy a pair of physical registers.
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
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}
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/// storeRegToStackSlot - Store the specified register of the given register
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/// class to the specified stack frame index. The store instruction is to be
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/// added to the given machine basic block before the specified machine
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/// instruction. If isKill is true, the register operand is the last use and
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/// must be marked kill.
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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llvm_unreachable("Target didn't implement "
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"TargetInstrInfo::storeRegToStackSlot!");
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}
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/// loadRegFromStackSlot - Load the specified register of the given register
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/// class from the specified stack frame index. The load instruction is to be
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/// added to the given machine basic block before the specified machine
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/// instruction.
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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llvm_unreachable("Target didn't implement "
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"TargetInstrInfo::loadRegFromStackSlot!");
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}
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/// expandPostRAPseudo - This function is called for all pseudo instructions
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/// that remain after register allocation. Many pseudo instructions are
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/// created to help register allocation. This is the place to convert them
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/// into real instructions. The target can edit MI in place, or it can insert
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/// new instructions and erase MI. The function should return true if
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/// anything was changed.
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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return false;
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}
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/// emitFrameIndexDebugValue - Emit a target-dependent form of
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/// DBG_VALUE encoding the address of a frame index. Addresses would
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/// normally be lowered the same way as other addresses on the target,
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/// e.g. in load instructions. For targets that do not support this
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/// the debug info is simply lost.
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/// If you add this for a target you should handle this DBG_VALUE in the
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/// target-specific AsmPrinter code as well; you will probably get invalid
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/// assembly output if you don't.
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virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx,
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uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc dl) const {
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return 0;
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned.
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/// The new instruction is inserted before MI, and the client is responsible
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/// for removing the old instruction.
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MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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protected:
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/// foldMemoryOperandImpl - Target-dependent implementation for
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/// foldMemoryOperand. Target-independent code in foldMemoryOperand will
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/// take care of adding a MachineMemOperand to the newly created instruction.
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
|
|
int FrameIndex) const {
|
|
return 0;
|
|
}
|
|
|
|
/// foldMemoryOperandImpl - Target-dependent implementation for
|
|
/// foldMemoryOperand. Target-independent code in foldMemoryOperand will
|
|
/// take care of adding a MachineMemOperand to the newly created instruction.
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr* LoadMI) const {
|
|
return 0;
|
|
}
|
|
|
|
public:
|
|
/// canFoldMemoryOperand - Returns true for the specified load / store if
|
|
/// folding is possible.
|
|
virtual
|
|
bool canFoldMemoryOperand(const MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops) const =0;
|
|
|
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
|
/// a store or a load and a store into two or more instruction. If this is
|
|
/// possible, returns true as well as the new instructions by reference.
|
|
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
|
return false;
|
|
}
|
|
|
|
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
SmallVectorImpl<SDNode*> &NewNodes) const {
|
|
return false;
|
|
}
|
|
|
|
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
|
/// instruction after load / store are unfolded from an instruction of the
|
|
/// specified opcode. It returns zero if the specified unfolding is not
|
|
/// possible. If LoadRegIndex is non-null, it is filled in with the operand
|
|
/// index of the operand which will hold the register holding the loaded
|
|
/// value.
|
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|
bool UnfoldLoad, bool UnfoldStore,
|
|
unsigned *LoadRegIndex = 0) const {
|
|
return 0;
|
|
}
|
|
|
|
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
|
|
/// to determine if two loads are loading from the same base address. It
|
|
/// should only return true if the base pointers are the same and the
|
|
/// only differences between the two addresses are the offset. It also returns
|
|
/// the offsets by reference.
|
|
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
|
|
int64_t &Offset1, int64_t &Offset2) const {
|
|
return false;
|
|
}
|
|
|
|
/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
|
|
/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
|
|
/// be scheduled togther. On some targets if two loads are loading from
|
|
/// addresses in the same cache line, it's better if they are scheduled
|
|
/// together. This function takes two integers that represent the load offsets
|
|
/// from the common base address. It returns true if it decides it's desirable
|
|
/// to schedule the two loads together. "NumLoads" is the number of loads that
|
|
/// have already been scheduled after Load1.
|
|
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
|
int64_t Offset1, int64_t Offset2,
|
|
unsigned NumLoads) const {
|
|
return false;
|
|
}
|
|
|
|
/// ReverseBranchCondition - Reverses the branch condition of the specified
|
|
/// condition list, returning false on success and true if it cannot be
|
|
/// reversed.
|
|
virtual
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
|
return true;
|
|
}
|
|
|
|
/// insertNoop - Insert a noop into the instruction stream at the specified
|
|
/// point.
|
|
virtual void insertNoop(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const;
|
|
|
|
|
|
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
|
|
virtual void getNoopForMachoTarget(MCInst &NopInst) const {
|
|
// Default to just using 'nop' string.
|
|
}
|
|
|
|
|
|
/// isPredicated - Returns true if the instruction is already predicated.
|
|
///
|
|
virtual bool isPredicated(const MachineInstr *MI) const {
|
|
return false;
|
|
}
|
|
|
|
/// isUnpredicatedTerminator - Returns true if the instruction is a
|
|
/// terminator instruction that has not been predicated.
|
|
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0;
|
|
|
|
/// PredicateInstruction - Convert the instruction into a predicated
|
|
/// instruction. It returns true if the operation was successful.
|
|
virtual
|
|
bool PredicateInstruction(MachineInstr *MI,
|
|
const SmallVectorImpl<MachineOperand> &Pred) const = 0;
|
|
|
|
/// SubsumesPredicate - Returns true if the first specified predicate
|
|
/// subsumes the second, e.g. GE subsumes GT.
|
|
virtual
|
|
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
|
const SmallVectorImpl<MachineOperand> &Pred2) const {
|
|
return false;
|
|
}
|
|
|
|
/// DefinesPredicate - If the specified instruction defines any predicate
|
|
/// or condition code register(s) used for predication, returns true as well
|
|
/// as the definition predicate(s) by reference.
|
|
virtual bool DefinesPredicate(MachineInstr *MI,
|
|
std::vector<MachineOperand> &Pred) const {
|
|
return false;
|
|
}
|
|
|
|
/// isPredicable - Return true if the specified instruction can be predicated.
|
|
/// By default, this returns true for every instruction with a
|
|
/// PredicateOperand.
|
|
virtual bool isPredicable(MachineInstr *MI) const {
|
|
return MI->getDesc().isPredicable();
|
|
}
|
|
|
|
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
|
|
/// instruction that defines the specified register class.
|
|
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
|
|
return true;
|
|
}
|
|
|
|
/// isSchedulingBoundary - Test if the given instruction should be
|
|
/// considered a scheduling boundary. This primarily includes labels and
|
|
/// terminators.
|
|
virtual bool isSchedulingBoundary(const MachineInstr *MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const = 0;
|
|
|
|
/// Measure the specified inline asm to determine an approximation of its
|
|
/// length.
|
|
virtual unsigned getInlineAsmLength(const char *Str,
|
|
const MCAsmInfo &MAI) const;
|
|
|
|
/// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
|
|
/// use for this target when scheduling the machine instructions before
|
|
/// register allocation.
|
|
virtual ScheduleHazardRecognizer*
|
|
CreateTargetHazardRecognizer(const TargetMachine *TM,
|
|
const ScheduleDAG *DAG) const = 0;
|
|
|
|
/// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
|
|
/// to use for this target when scheduling the machine instructions before
|
|
/// register allocation.
|
|
virtual ScheduleHazardRecognizer*
|
|
CreateTargetMIHazardRecognizer(const InstrItineraryData*,
|
|
const ScheduleDAG *DAG) const = 0;
|
|
|
|
/// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
|
|
/// recognizer to use for this target when scheduling the machine instructions
|
|
/// after register allocation.
|
|
virtual ScheduleHazardRecognizer*
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
|
|
const ScheduleDAG *DAG) const = 0;
|
|
|
|
/// AnalyzeCompare - For a comparison instruction, return the source register
|
|
/// in SrcReg and the value it compares against in CmpValue. Return true if
|
|
/// the comparison instruction can be analyzed.
|
|
virtual bool AnalyzeCompare(const MachineInstr *MI,
|
|
unsigned &SrcReg, int &Mask, int &Value) const {
|
|
return false;
|
|
}
|
|
|
|
/// OptimizeCompareInstr - See if the comparison instruction can be converted
|
|
/// into something more efficient. E.g., on ARM most instructions can set the
|
|
/// flags register, obviating the need for a separate CMP.
|
|
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
|
|
unsigned SrcReg, int Mask, int Value,
|
|
const MachineRegisterInfo *MRI) const {
|
|
return false;
|
|
}
|
|
|
|
/// OptimizeSubInstr - See if the SUB instruction can be converted into
|
|
/// something more efficient E.g., on X86, we can replace SUB with CMP
|
|
/// if the actual result of SUB is not used.
|
|
virtual bool OptimizeSubInstr(MachineInstr *SubInstr,
|
|
const MachineRegisterInfo *MRI) const {
|
|
return false;
|
|
}
|
|
|
|
/// FoldImmediate - 'Reg' is known to be defined by a move immediate
|
|
/// instruction, try to fold the immediate into the use instruction.
|
|
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
|
|
unsigned Reg, MachineRegisterInfo *MRI) const {
|
|
return false;
|
|
}
|
|
|
|
/// getNumMicroOps - Return the number of u-operations the given machine
|
|
/// instruction will be decoded to on the target cpu.
|
|
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
|
|
const MachineInstr *MI) const;
|
|
|
|
/// isZeroCost - Return true for pseudo instructions that don't consume any
|
|
/// machine resources in their current form. These are common cases that the
|
|
/// scheduler should consider free, rather than conservatively handling them
|
|
/// as instructions with no itinerary.
|
|
bool isZeroCost(unsigned Opcode) const {
|
|
return Opcode <= TargetOpcode::COPY;
|
|
}
|
|
|
|
/// getOperandLatency - Compute and return the use operand latency of a given
|
|
/// pair of def and use.
|
|
/// In most cases, the static scheduling itinerary was enough to determine the
|
|
/// operand latency. But it may not be possible for instructions with variable
|
|
/// number of defs / uses.
|
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
const MachineInstr *UseMI, unsigned UseIdx) const;
|
|
|
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
|
SDNode *DefNode, unsigned DefIdx,
|
|
SDNode *UseNode, unsigned UseIdx) const = 0;
|
|
|
|
/// getOutputLatency - Compute and return the output dependency latency of a
|
|
/// a given pair of defs which both target the same register. This is usually
|
|
/// one.
|
|
virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
const MachineInstr *DepMI) const {
|
|
return 1;
|
|
}
|
|
|
|
/// getInstrLatency - Compute the instruction latency of a given instruction.
|
|
/// If the instruction has higher cost when predicated, it's returned via
|
|
/// PredCost.
|
|
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *MI,
|
|
unsigned *PredCost = 0) const;
|
|
|
|
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
|
SDNode *Node) const = 0;
|
|
|
|
/// isHighLatencyDef - Return true if this opcode has high latency to its
|
|
/// result.
|
|
virtual bool isHighLatencyDef(int opc) const { return false; }
|
|
|
|
/// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
|
|
/// and an use in the current loop, return true if the target considered
|
|
/// it 'high'. This is used by optimization passes such as machine LICM to
|
|
/// determine whether it makes sense to hoist an instruction out even in
|
|
/// high register pressure situation.
|
|
virtual
|
|
bool hasHighOperandLatency(const InstrItineraryData *ItinData,
|
|
const MachineRegisterInfo *MRI,
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
const MachineInstr *UseMI, unsigned UseIdx) const {
|
|
return false;
|
|
}
|
|
|
|
/// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
|
|
/// if the target considered it 'low'.
|
|
virtual
|
|
bool hasLowDefLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, unsigned DefIdx) const;
|
|
|
|
/// verifyInstruction - Perform target specific instruction verification.
|
|
virtual
|
|
bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
|
|
return true;
|
|
}
|
|
|
|
/// getExecutionDomain - Return the current execution domain and bit mask of
|
|
/// possible domains for instruction.
|
|
///
|
|
/// Some micro-architectures have multiple execution domains, and multiple
|
|
/// opcodes that perform the same operation in different domains. For
|
|
/// example, the x86 architecture provides the por, orps, and orpd
|
|
/// instructions that all do the same thing. There is a latency penalty if a
|
|
/// register is written in one domain and read in another.
|
|
///
|
|
/// This function returns a pair (domain, mask) containing the execution
|
|
/// domain of MI, and a bit mask of possible domains. The setExecutionDomain
|
|
/// function can be used to change the opcode to one of the domains in the
|
|
/// bit mask. Instructions whose execution domain can't be changed should
|
|
/// return a 0 mask.
|
|
///
|
|
/// The execution domain numbers don't have any special meaning except domain
|
|
/// 0 is used for instructions that are not associated with any interesting
|
|
/// execution domain.
|
|
///
|
|
virtual std::pair<uint16_t, uint16_t>
|
|
getExecutionDomain(const MachineInstr *MI) const {
|
|
return std::make_pair(0, 0);
|
|
}
|
|
|
|
/// setExecutionDomain - Change the opcode of MI to execute in Domain.
|
|
///
|
|
/// The bit (1 << Domain) must be set in the mask returned from
|
|
/// getExecutionDomain(MI).
|
|
///
|
|
virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
|
|
|
|
|
|
/// getPartialRegUpdateClearance - Returns the preferred minimum clearance
|
|
/// before an instruction with an unwanted partial register update.
|
|
///
|
|
/// Some instructions only write part of a register, and implicitly need to
|
|
/// read the other parts of the register. This may cause unwanted stalls
|
|
/// preventing otherwise unrelated instructions from executing in parallel in
|
|
/// an out-of-order CPU.
|
|
///
|
|
/// For example, the x86 instruction cvtsi2ss writes its result to bits
|
|
/// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
|
|
/// the instruction needs to wait for the old value of the register to become
|
|
/// available:
|
|
///
|
|
/// addps %xmm1, %xmm0
|
|
/// movaps %xmm0, (%rax)
|
|
/// cvtsi2ss %rbx, %xmm0
|
|
///
|
|
/// In the code above, the cvtsi2ss instruction needs to wait for the addps
|
|
/// instruction before it can issue, even though the high bits of %xmm0
|
|
/// probably aren't needed.
|
|
///
|
|
/// This hook returns the preferred clearance before MI, measured in
|
|
/// instructions. Other defs of MI's operand OpNum are avoided in the last N
|
|
/// instructions before MI. It should only return a positive value for
|
|
/// unwanted dependencies. If the old bits of the defined register have
|
|
/// useful values, or if MI is determined to otherwise read the dependency,
|
|
/// the hook should return 0.
|
|
///
|
|
/// The unwanted dependency may be handled by:
|
|
///
|
|
/// 1. Allocating the same register for an MI def and use. That makes the
|
|
/// unwanted dependency identical to a required dependency.
|
|
///
|
|
/// 2. Allocating a register for the def that has no defs in the previous N
|
|
/// instructions.
|
|
///
|
|
/// 3. Calling breakPartialRegDependency() with the same arguments. This
|
|
/// allows the target to insert a dependency breaking instruction.
|
|
///
|
|
virtual unsigned
|
|
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
|
|
const TargetRegisterInfo *TRI) const {
|
|
// The default implementation returns 0 for no partial register dependency.
|
|
return 0;
|
|
}
|
|
|
|
/// breakPartialRegDependency - Insert a dependency-breaking instruction
|
|
/// before MI to eliminate an unwanted dependency on OpNum.
|
|
///
|
|
/// If it wasn't possible to avoid a def in the last N instructions before MI
|
|
/// (see getPartialRegUpdateClearance), this hook will be called to break the
|
|
/// unwanted dependency.
|
|
///
|
|
/// On x86, an xorps instruction can be used as a dependency breaker:
|
|
///
|
|
/// addps %xmm1, %xmm0
|
|
/// movaps %xmm0, (%rax)
|
|
/// xorps %xmm0, %xmm0
|
|
/// cvtsi2ss %rbx, %xmm0
|
|
///
|
|
/// An <imp-kill> operand should be added to MI if an instruction was
|
|
/// inserted. This ties the instructions together in the post-ra scheduler.
|
|
///
|
|
virtual void
|
|
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
|
|
const TargetRegisterInfo *TRI) const {}
|
|
|
|
/// Create machine specific model for scheduling.
|
|
virtual DFAPacketizer*
|
|
CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const {
|
|
return NULL;
|
|
}
|
|
|
|
private:
|
|
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
|
|
};
|
|
|
|
/// TargetInstrInfoImpl - This is the default implementation of
|
|
/// TargetInstrInfo, which just provides a couple of default implementations
|
|
/// for various methods. This separated out because it is implemented in
|
|
/// libcodegen, not in libtarget.
|
|
class TargetInstrInfoImpl : public TargetInstrInfo {
|
|
protected:
|
|
TargetInstrInfoImpl(int CallFrameSetupOpcode = -1,
|
|
int CallFrameDestroyOpcode = -1)
|
|
: TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
|
|
public:
|
|
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
|
|
MachineBasicBlock *NewDest) const;
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI,
|
|
bool NewMI = false) const;
|
|
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
|
|
unsigned &SrcOpIdx2) const;
|
|
virtual bool canFoldMemoryOperand(const MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops) const;
|
|
virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
|
|
const MachineMemOperand *&MMO,
|
|
int &FrameIndex) const;
|
|
virtual bool hasStoreToStackSlot(const MachineInstr *MI,
|
|
const MachineMemOperand *&MMO,
|
|
int &FrameIndex) const;
|
|
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
|
|
virtual bool PredicateInstruction(MachineInstr *MI,
|
|
const SmallVectorImpl<MachineOperand> &Pred) const;
|
|
virtual void reMaterialize(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, unsigned SubReg,
|
|
const MachineInstr *Orig,
|
|
const TargetRegisterInfo &TRI) const;
|
|
virtual MachineInstr *duplicate(MachineInstr *Orig,
|
|
MachineFunction &MF) const;
|
|
virtual bool produceSameValue(const MachineInstr *MI0,
|
|
const MachineInstr *MI1,
|
|
const MachineRegisterInfo *MRI) const;
|
|
virtual bool isSchedulingBoundary(const MachineInstr *MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const;
|
|
using TargetInstrInfo::getOperandLatency;
|
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
|
SDNode *DefNode, unsigned DefIdx,
|
|
SDNode *UseNode, unsigned UseIdx) const;
|
|
using TargetInstrInfo::getInstrLatency;
|
|
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
|
SDNode *Node) const;
|
|
|
|
bool usePreRAHazardRecognizer() const;
|
|
|
|
virtual ScheduleHazardRecognizer *
|
|
CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const;
|
|
|
|
virtual ScheduleHazardRecognizer *
|
|
CreateTargetMIHazardRecognizer(const InstrItineraryData*,
|
|
const ScheduleDAG*) const;
|
|
|
|
virtual ScheduleHazardRecognizer *
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
|
|
const ScheduleDAG*) const;
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|