James Molloy fca7f5c585 [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian. ... The AAPCS states that values passed in registers must have a value as though they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is, loading scalars to vector registers and loading 1-element vectors is equivalent. The logic implemented here is to ensure that at all call boundaries and during formal argument lowering all vectors are treated as their bitwidth-based floating point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64, v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be generated during code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-07 12:33:41 +00:00
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AArch64	[ARM64-BE] Make big endian (scalar) argument passing work correctly.	2014-05-07 11:28:36 +00:00
ARM	Allow using normal .eh_frame based unwinding on ARM. Use the same	2014-05-07 07:49:34 +00:00
ARM64	[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.	2014-05-07 12:33:41 +00:00
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X86	[X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).	2014-05-06 17:09:03 +00:00
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