llvm-6502/test/CodeGen/Hexagon/vect/vect-vaddw.ll
Krzysztof Parzyszek 07121ea974 [Hexagon] Add support for vector instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232728 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-19 16:33:08 +00:00

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181 B
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vaddw
define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
entry:
%0 = add <2 x i32> %a, %b
ret <2 x i32> %0
}