mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
3.4 KiB
LLVM
132 lines
3.4 KiB
LLVM
; Test 32-bit subtraction in which the second operand is a sign-extended
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; i16 memory value.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the SH range.
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define i32 @f1(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: sh %r2, 0(%r3)
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; CHECK: br %r14
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%half = load i16 , i16 *%src
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the aligned SH range.
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define i32 @f2(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: sh %r2, 4094(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 2047
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword up, which should use SHY instead of SH.
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define i32 @f3(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: shy %r2, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 2048
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the aligned SHY range.
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define i32 @f4(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: shy %r2, 524286(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262143
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f5(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r3, 524288
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; CHECK: sh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262144
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the negative aligned SHY range.
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define i32 @f6(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: shy %r2, -2(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -1
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the low end of the SHY range.
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define i32 @f7(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: shy %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262144
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f8(i32 %lhs, i16 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r3, -524290
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; CHECK: sh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262145
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check that SH allows an index.
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define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
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; CHECK-LABEL: f9:
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; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%sub1 = add i64 %src, %index
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%sub2 = add i64 %sub1, 4094
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%ptr = inttoptr i64 %sub2 to i16 *
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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; Check that SHY allows an index.
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define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%sub1 = add i64 %src, %index
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%sub2 = add i64 %sub1, 4096
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%ptr = inttoptr i64 %sub2 to i16 *
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%half = load i16 , i16 *%ptr
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%rhs = sext i16 %half to i32
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%res = sub i32 %lhs, %rhs
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ret i32 %res
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}
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