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https://github.com/c64scene-ar/llvm-6502.git
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0543dab791
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.4 KiB
LLVM
77 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=mips -relocation-model=static | \
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; RUN: FileCheck %s -check-prefix=STATIC-O32
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; RUN: llc < %s -march=mips -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefix=PIC-O32
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; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips4 | \
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; RUN: FileCheck %s -check-prefix=N64
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; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips4 | \
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; RUN: FileCheck %s -check-prefix=N64
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; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \
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; RUN: FileCheck %s -check-prefix=N64
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; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \
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; RUN: FileCheck %s -check-prefix=N64
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define i32 @main() nounwind readnone {
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entry:
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%x = alloca i32, align 4 ; <i32*> [#uses=2]
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store volatile i32 2, i32* %x, align 4
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%0 = load volatile i32* %x, align 4 ; <i32> [#uses=1]
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; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
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; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
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; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
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; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
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; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
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; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
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; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
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; PIC-O32: jr $[[R5]]
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; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3
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; N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0)
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; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
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; N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]])
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; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
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; N64: jr $[[R5]]
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switch i32 %0, label %bb4 [
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i32 0, label %bb5
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i32 1, label %bb1
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i32 2, label %bb2
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i32 3, label %bb3
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]
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bb1: ; preds = %entry
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ret i32 2
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bb2: ; preds = %entry
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ret i32 0
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bb3: ; preds = %entry
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ret i32 3
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bb4: ; preds = %entry
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ret i32 4
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bb5: ; preds = %entry
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ret i32 1
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}
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; STATIC-O32: .align 2
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; STATIC-O32: $JTI0_0:
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; PIC-O32: .align 2
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; PIC-O32: $JTI0_0:
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; N64: .align 3
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; N64: $JTI0_0:
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; N64: .gpdword
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; N64: .gpdword
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; N64: .gpdword
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; N64: .gpdword
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