mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
3.5 KiB
LLVM
138 lines
3.5 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=v7
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi | FileCheck %s --check-prefix=prev6
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi | FileCheck %s --check-prefix=prev6
|
|
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7
|
|
|
|
; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
|
|
; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
|
|
; using two shifts.
|
|
|
|
; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
|
|
; and therefore must set flags. {{s?}} below denotes this, instead of
|
|
; duplicating tests.
|
|
|
|
; zext
|
|
|
|
define i8 @zext_1_8(i1 %a) nounwind ssp {
|
|
; v7-LABEL: zext_1_8:
|
|
; v7: and r0, r0, #1
|
|
; prev6-LABEL: zext_1_8:
|
|
; prev6: and r0, r0, #1
|
|
%r = zext i1 %a to i8
|
|
ret i8 %r
|
|
}
|
|
|
|
define i16 @zext_1_16(i1 %a) nounwind ssp {
|
|
; v7-LABEL: zext_1_16:
|
|
; v7: and r0, r0, #1
|
|
; prev6-LABEL: zext_1_16:
|
|
; prev6: and r0, r0, #1
|
|
%r = zext i1 %a to i16
|
|
ret i16 %r
|
|
}
|
|
|
|
define i32 @zext_1_32(i1 %a) nounwind ssp {
|
|
; v7-LABEL: zext_1_32:
|
|
; v7: and r0, r0, #1
|
|
; prev6-LABEL: zext_1_32:
|
|
; prev6: and r0, r0, #1
|
|
%r = zext i1 %a to i32
|
|
ret i32 %r
|
|
}
|
|
|
|
define i16 @zext_8_16(i8 %a) nounwind ssp {
|
|
; v7-LABEL: zext_8_16:
|
|
; v7: and r0, r0, #255
|
|
; prev6-LABEL: zext_8_16:
|
|
; prev6: and r0, r0, #255
|
|
%r = zext i8 %a to i16
|
|
ret i16 %r
|
|
}
|
|
|
|
define i32 @zext_8_32(i8 %a) nounwind ssp {
|
|
; v7-LABEL: zext_8_32:
|
|
; v7: and r0, r0, #255
|
|
; prev6-LABEL: zext_8_32:
|
|
; prev6: and r0, r0, #255
|
|
%r = zext i8 %a to i32
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @zext_16_32(i16 %a) nounwind ssp {
|
|
; v7-LABEL: zext_16_32:
|
|
; v7: uxth r0, r0
|
|
; prev6-LABEL: zext_16_32:
|
|
; prev6: lsl{{s?}} r0, r0, #16
|
|
; prev6: lsr{{s?}} r0, r0, #16
|
|
%r = zext i16 %a to i32
|
|
ret i32 %r
|
|
}
|
|
|
|
; sext
|
|
|
|
define i8 @sext_1_8(i1 %a) nounwind ssp {
|
|
; v7-LABEL: sext_1_8:
|
|
; v7: lsl{{s?}} r0, r0, #31
|
|
; v7: asr{{s?}} r0, r0, #31
|
|
; prev6-LABEL: sext_1_8:
|
|
; prev6: lsl{{s?}} r0, r0, #31
|
|
; prev6: asr{{s?}} r0, r0, #31
|
|
%r = sext i1 %a to i8
|
|
ret i8 %r
|
|
}
|
|
|
|
define i16 @sext_1_16(i1 %a) nounwind ssp {
|
|
; v7-LABEL: sext_1_16:
|
|
; v7: lsl{{s?}} r0, r0, #31
|
|
; v7: asr{{s?}} r0, r0, #31
|
|
; prev6-LABEL: sext_1_16:
|
|
; prev6: lsl{{s?}} r0, r0, #31
|
|
; prev6: asr{{s?}} r0, r0, #31
|
|
%r = sext i1 %a to i16
|
|
ret i16 %r
|
|
}
|
|
|
|
define i32 @sext_1_32(i1 %a) nounwind ssp {
|
|
; v7-LABEL: sext_1_32:
|
|
; v7: lsl{{s?}} r0, r0, #31
|
|
; v7: asr{{s?}} r0, r0, #31
|
|
; prev6-LABEL: sext_1_32:
|
|
; prev6: lsl{{s?}} r0, r0, #31
|
|
; prev6: asr{{s?}} r0, r0, #31
|
|
%r = sext i1 %a to i32
|
|
ret i32 %r
|
|
}
|
|
|
|
define i16 @sext_8_16(i8 %a) nounwind ssp {
|
|
; v7-LABEL: sext_8_16:
|
|
; v7: sxtb r0, r0
|
|
; prev6-LABEL: sext_8_16:
|
|
; prev6: lsl{{s?}} r0, r0, #24
|
|
; prev6: asr{{s?}} r0, r0, #24
|
|
%r = sext i8 %a to i16
|
|
ret i16 %r
|
|
}
|
|
|
|
define i32 @sext_8_32(i8 %a) nounwind ssp {
|
|
; v7-LABEL: sext_8_32:
|
|
; v7: sxtb r0, r0
|
|
; prev6-LABEL: sext_8_32:
|
|
; prev6: lsl{{s?}} r0, r0, #24
|
|
; prev6: asr{{s?}} r0, r0, #24
|
|
%r = sext i8 %a to i32
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @sext_16_32(i16 %a) nounwind ssp {
|
|
; v7-LABEL: sext_16_32:
|
|
; v7: sxth r0, r0
|
|
; prev6-LABEL: sext_16_32:
|
|
; prev6: lsl{{s?}} r0, r0, #16
|
|
; prev6: asr{{s?}} r0, r0, #16
|
|
%r = sext i16 %a to i32
|
|
ret i32 %r
|
|
}
|