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https://github.com/c64scene-ar/llvm-6502.git
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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
407 lines
13 KiB
C++
407 lines
13 KiB
C++
//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the XCore implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreInstrInfo.h"
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#include "XCore.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR
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#include "XCoreGenInstrInfo.inc"
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namespace llvm {
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namespace XCore {
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// XCore Condition Codes
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enum CondCode {
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COND_TRUE,
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COND_FALSE,
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COND_INVALID
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};
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}
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}
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using namespace llvm;
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XCoreInstrInfo::XCoreInstrInfo()
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: XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
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RI(*this) {
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}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned
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XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::LDWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned
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XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::STWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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static inline bool IsBRU(unsigned BrOpc) {
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return BrOpc == XCore::BRFU_u6
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|| BrOpc == XCore::BRFU_lu6
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|| BrOpc == XCore::BRBU_u6
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|| BrOpc == XCore::BRBU_lu6;
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}
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static inline bool IsBRT(unsigned BrOpc) {
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return BrOpc == XCore::BRFT_ru6
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|| BrOpc == XCore::BRFT_lru6
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|| BrOpc == XCore::BRBT_ru6
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|| BrOpc == XCore::BRBT_lru6;
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}
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static inline bool IsBRF(unsigned BrOpc) {
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return BrOpc == XCore::BRFF_ru6
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|| BrOpc == XCore::BRFF_lru6
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|| BrOpc == XCore::BRBF_ru6
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|| BrOpc == XCore::BRBF_lru6;
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}
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static inline bool IsCondBranch(unsigned BrOpc) {
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return IsBRF(BrOpc) || IsBRT(BrOpc);
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}
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static inline bool IsBR_JT(unsigned BrOpc) {
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return BrOpc == XCore::BR_JT
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|| BrOpc == XCore::BR_JT32;
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}
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/// GetCondFromBranchOpc - Return the XCore CC that matches
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/// the correspondent Branch instruction opcode.
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static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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if (IsBRT(BrOpc)) {
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return XCore::COND_TRUE;
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} else if (IsBRF(BrOpc)) {
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return XCore::COND_FALSE;
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} else {
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return XCore::COND_INVALID;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case XCore::COND_TRUE : return XCore::BRFT_lru6;
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case XCore::COND_FALSE : return XCore::BRFF_lru6;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case XCore::COND_TRUE : return XCore::COND_FALSE;
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case XCore::COND_FALSE : return XCore::COND_TRUE;
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}
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}
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch and it falls through to
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/// an successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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/// 4. If this block ends with an conditional branch and an unconditional
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/// block, it returns the 'true' destination in TBB, the 'false' destination
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/// in FBB, and a list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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bool
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XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (IsBRU(LastInst->getOpcode())) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == XCore::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Conditional branch
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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Cond.push_back(LastInst->getOperand(0));
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return false;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
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// If the block ends with conditional branch followed by unconditional,
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// handle it.
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if (BranchCode != XCore::COND_INVALID
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&& IsBRU(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if (IsBRU(SecondLastInst->getOpcode()) &&
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IsBRU(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Likewise if it ends with a branch table followed by an unconditional branch.
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if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return true;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned
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XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL)const{
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Unexpected number of components!");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch
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BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
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} else {
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// Conditional branch.
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unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
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BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
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.addMBB(TBB);
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}
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return 1;
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}
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// Two-way Conditional branch.
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assert(Cond.size() == 2 && "Unexpected number of components!");
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unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
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BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
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.addMBB(TBB);
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BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
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return 2;
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}
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unsigned
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XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (!IsCondBranch(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
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bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
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if (GRDest && GRSrc) {
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BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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return;
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}
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if (GRDest && SrcReg == XCore::SP) {
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BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
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return;
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}
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if (DestReg == XCore::SP && GRSrc) {
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BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, get(XCore::STWFI))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIndex)
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.addImm(0);
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}
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void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
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.addFrameIndex(FrameIndex)
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.addImm(0);
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}
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MachineInstr*
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XCoreInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
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uint64_t Offset, const MDNode *MDPtr,
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DebugLoc DL) const {
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
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.addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
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return &*MIB;
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool XCoreInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 2) &&
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"Invalid XCore branch condition!");
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Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
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return false;
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}
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