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fd1b7c778c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70703 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.8 KiB
TableGen
46 lines
1.8 KiB
TableGen
//===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the MSP430 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "MSP430InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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//===----------------------------------------------------------------------===//
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// Real Instructions
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//===----------------------------------------------------------------------===//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RETI: Pseudo<(outs), (ins), "reti", [(retflag)]>;
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}
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