mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
8d1ffbd1ad
Based on the patch by Brian Lucas! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91175 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
2.5 KiB
LLVM
117 lines
2.5 KiB
LLVM
; RUN: llc -march=msp430 < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
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target triple = "msp430-generic-generic"
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define i16 @sccweqand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp eq i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: sccweqand:
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; CHECK: bit.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwneand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: sccwneand:
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; CHECK: bit.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwne(i16 %a, i16 %b) nounwind {
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%t1 = icmp ne i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwne:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: rra.w r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccweq(i16 %a, i16 %b) nounwind {
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%t1 = icmp eq i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccweq:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: rra.w r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwugt(i16 %a, i16 %b) nounwind {
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%t1 = icmp ugt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwugt:
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; CHECK: cmp.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwuge(i16 %a, i16 %b) nounwind {
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%t1 = icmp uge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwuge:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwult(i16 %a, i16 %b) nounwind {
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%t1 = icmp ult i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwult:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwule(i16 %a, i16 %b) nounwind {
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%t1 = icmp ule i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwule:
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; CHECK: cmp.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
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%t1 = icmp sgt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsge(i16 %a, i16 %b) nounwind {
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%t1 = icmp sge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwslt(i16 %a, i16 %b) nounwind {
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%t1 = icmp slt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsle(i16 %a, i16 %b) nounwind {
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%t1 = icmp sle i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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