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https://github.com/c64scene-ar/llvm-6502.git
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1cbca515b6
target independent.
Most of the x86 specific stackmap/patchpoint handling was necessitated by the
use of the native address-mode format for frame index operands. PEI has now
been modified to treat stackmap/patchpoint similarly to DEBUG_INFO, allowing
us to use a simple, platform independent register/offset pair for frame
indexes on stackmap/patchpoints.
Notes:
- Folding is now platform independent and automatically supported.
- Emiting patchpoints with direct memory references now just involves calling
the TargetLoweringBase::emitPatchPoint utility method from the target's
XXXTargetLowering::EmitInstrWithCustomInserter method. (See
X86TargetLowering for an example).
- No more ugly platform-specific operand parsers.
This patch shouldn't change the generated output for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195944 91177308-0d34-0410-b5e6-96231b3b80d8
996 lines
40 KiB
C++
996 lines
40 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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namespace llvm {
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// BSF - Bit scan forward.
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/// BSR - Bit scan reverse.
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BSF,
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BSR,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// FAND - Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// FOR - Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// FANDN - Bitwise logical ANDNOT of floating point values. This
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/// corresponds to X86::ANDNPS or X86::ANDNPD.
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FANDN,
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/// FSRL - Bitwise logical right shift of floating point values. These
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/// corresponds to X86::PSRLDQ.
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FSRL,
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/// CALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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CALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 bit-test instructions.
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BT,
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/// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
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/// operand, usually produced by a CMP instruction.
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SETCC,
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// Same as SETCC except it's materialized with a sbb and the value is all
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// one's or all zero's.
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SETCC_CARRY, // R = carry_bit ? ~0 : 0
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/// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
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/// Operands are two FP values to compare; result is a mask of
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/// 0s or 1s. Generally DTRT for C/C++ with NaNs.
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FSETCCss, FSETCCsd,
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/// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
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/// result in an integer GPR. Needs masking for scalar result.
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FGETSIGNx86,
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/// X86 conditional moves. Operand 0 and operand 1 are the two values
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/// to select from. Operand 2 is the condition code, and operand 3 is the
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/// flag operand produced by a CMP or TEST instruction. It also writes a
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/// flag result.
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CMOV,
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/// X86 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 0 is the chain operand, operand
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/// 1 is the number of bytes of stack to pop.
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RET_FLAG,
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/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// GlobalBaseReg - On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// Wrapper - A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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/// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
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/// to an MMX vector. If you think this is too close to the previous
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/// mnemonic, so do I; blame Intel.
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MOVDQ2Q,
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/// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
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/// vector to a GPR.
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MMX_MOVD2W,
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/// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// INSERTPS - Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW, MMX_PINSRW,
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/// PSHUFB - Shuffle 16 8-bit values within a vector.
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PSHUFB,
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/// ANDNP - Bitwise Logical AND NOT of Packed FP values.
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ANDNP,
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/// PSIGN - Copy integer sign.
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PSIGN,
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/// BLENDV - Blend where the selector is a register.
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BLENDV,
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/// BLENDI - Blend where the selector is an immediate.
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BLENDI,
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// SUBUS - Integer sub with unsigned saturation.
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SUBUS,
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/// HADD - Integer horizontal add.
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HADD,
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/// HSUB - Integer horizontal sub.
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HSUB,
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/// FHADD - Floating point horizontal add.
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FHADD,
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/// FHSUB - Floating point horizontal sub.
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FHSUB,
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/// UMAX, UMIN - Unsigned integer max and min.
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UMAX, UMIN,
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/// SMAX, SMIN - Signed integer max and min.
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SMAX, SMIN,
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/// FMAX, FMIN - Floating point max and min.
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///
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FMAX, FMIN,
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/// FMAXC, FMINC - Commutative FMIN and FMAX.
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FMAXC, FMINC,
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/// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
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/// approximation. Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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// TLSADDR - Thread Local Storage.
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TLSADDR,
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// TLSBASEADDR - Thread Local Storage. A call to get the start address
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// of the TLS block for the current module.
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TLSBASEADDR,
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// TLSCALL - Thread Local Storage. When calling to an OS provided
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// thunk at the address from an earlier relocation.
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TLSCALL,
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// EH_RETURN - Exception Handling helpers.
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EH_RETURN,
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// EH_SJLJ_SETJMP - SjLj exception handling setjmp.
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EH_SJLJ_SETJMP,
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// EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
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EH_SJLJ_LONGJMP,
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/// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
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/// the list of operands.
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TC_RETURN,
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VSEXT_MOVL - Vector move low and sign extend.
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VSEXT_MOVL,
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// VZEXT - Vector integer zero-extend.
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VZEXT,
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// VSEXT - Vector integer signed-extend.
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VSEXT,
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// VTRUNC - Vector integer truncate.
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VTRUNC,
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// VTRUNC - Vector integer truncate with mask.
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VTRUNCM,
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// VFPEXT - Vector FP extend.
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VFPEXT,
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// VFPROUND - Vector FP round.
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VFPROUND,
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// VSHL, VSRL - 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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// VSHL, VSRL, VSRA - Vector shift elements
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VSHL, VSRL, VSRA,
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// VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
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VSHLI, VSRLI, VSRAI,
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// CMPP - Vector packed double/float comparison.
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CMPP,
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// PCMP* - Vector integer comparisons.
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PCMPEQ, PCMPGT,
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// PCMP*M - Vector integer comparisons, the result is in a mask vector.
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PCMPEQM, PCMPGTM,
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/// CMPM, CMPMU - Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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CMPM,
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CMPMU,
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// ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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INC, DEC, OR, XOR, AND,
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BLSI, // BLSI - Extract lowest set isolated bit
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BLSMSK, // BLSMSK - Get mask up to lowest set bit
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BLSR, // BLSR - Reset lowest set bit
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BZHI, // BZHI - Zero high bits
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BEXTR, // BEXTR - Bit field extract
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UMUL, // LOW, HI, FLAGS = umul LHS, RHS
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// MUL_IMM - X86 specific multiply by immediate.
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MUL_IMM,
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// PTEST - Vector bitwise comparisons.
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PTEST,
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// TESTP - Vector packed fp sign bitwise comparisons.
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TESTP,
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// TESTM - Vector "test" in AVX-512, the result is in a mask vector.
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TESTM,
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// OR/AND test for masks
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KORTEST,
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KTEST,
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// Several flavors of instructions with vector shuffle behaviors.
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PALIGNR,
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PSHUFD,
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PSHUFHW,
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PSHUFLW,
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SHUFP,
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MOVDDUP,
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MOVSHDUP,
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MOVSLDUP,
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MOVLHPS,
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MOVLHPD,
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MOVHLPS,
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MOVLPS,
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MOVLPD,
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MOVSD,
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MOVSS,
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UNPCKL,
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UNPCKH,
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VPERMILP,
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VPERMV,
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VPERMV3,
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VPERMI,
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VPERM2X128,
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VBROADCAST,
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// masked broadcast
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VBROADCASTM,
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VINSERT,
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// PMULUDQ - Vector multiply packed unsigned doubleword integers
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PMULUDQ,
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// FMA nodes
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FMADD,
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FNMADD,
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FMSUB,
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FNMSUB,
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FMADDSUB,
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FMSUBADD,
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// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
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// according to %al. An operator is needed so that this can be expanded
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// with control flow.
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VASTART_SAVE_XMM_REGS,
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// WIN_ALLOCA - Windows's _chkstk call to do stack probing.
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WIN_ALLOCA,
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// SEG_ALLOCA - For allocating variable amounts of stack space when using
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// segmented stacks. Check if the current stacklet has enough space, and
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// falls back to heap allocation if not.
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SEG_ALLOCA,
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// WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
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WIN_FTOL,
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// Memory barrier
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MEMBARRIER,
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MFENCE,
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SFENCE,
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LFENCE,
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// FNSTSW16r - Store FP status word into i16 register.
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FNSTSW16r,
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// SAHF - Store contents of %ah into %eflags.
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SAHF,
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// RDRAND - Get a random integer and indicate whether it is valid in CF.
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RDRAND,
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// RDSEED - Get a NIST SP800-90B & C compliant random integer and
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// indicate whether it is valid in CF.
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RDSEED,
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// PCMP*STRI
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PCMPISTRI,
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PCMPESTRI,
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// XTEST - Test if in transactional execution.
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XTEST,
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// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
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// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
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// Atomic 64-bit binary operations.
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ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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ATOMSUB64_DAG,
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ATOMOR64_DAG,
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ATOMXOR64_DAG,
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMMAX64_DAG,
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ATOMMIN64_DAG,
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ATOMUMAX64_DAG,
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ATOMUMIN64_DAG,
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ATOMSWAP64_DAG,
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// LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
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LCMPXCHG_DAG,
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LCMPXCHG8_DAG,
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LCMPXCHG16_DAG,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// FNSTCW16m - Store FP control world into i16 memory.
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FNSTCW16m,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value
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/// and token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// VAARG_64 - This instruction grabs the address of the next argument
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/// from a va_list. (reads and modifies the va_list in memory)
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VAARG_64
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// WARNING: Do not add anything in the end unless you want the node to
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// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
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// thought as target memory ops!
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isVEXTRACT128Index - Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
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bool isVEXTRACT128Index(SDNode *N);
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/// isVINSERT128Index - Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF128, VINSERTI128 instructions.
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bool isVINSERT128Index(SDNode *N);
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/// isVEXTRACT256Index - Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
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bool isVEXTRACT256Index(SDNode *N);
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/// isVINSERT256Index - Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
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bool isVINSERT256Index(SDNode *N);
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/// getExtractVEXTRACT128Immediate - Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF128, VEXTRACTI128 instructions.
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unsigned getExtractVEXTRACT128Immediate(SDNode *N);
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/// getInsertVINSERT128Immediate - Return the appropriate
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/// immediate to insert at the specified INSERT_SUBVECTOR index
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/// with VINSERTF128, VINSERT128 instructions.
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unsigned getInsertVINSERT128Immediate(SDNode *N);
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/// getExtractVEXTRACT256Immediate - Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
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unsigned getExtractVEXTRACT256Immediate(SDNode *N);
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/// getInsertVINSERT256Immediate - Return the appropriate
|
|
/// immediate to insert at the specified INSERT_SUBVECTOR index
|
|
/// with VINSERTF64x4, VINSERTI64x4 instructions.
|
|
unsigned getInsertVINSERT256Immediate(SDNode *N);
|
|
|
|
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
|
|
/// constant +0.0.
|
|
bool isZeroNode(SDValue Elt);
|
|
|
|
/// isOffsetSuitableForCodeModel - Returns true of the given offset can be
|
|
/// fit into displacement field of the instruction.
|
|
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
|
|
bool hasSymbolicDisplacement = true);
|
|
|
|
|
|
/// isCalleePop - Determines whether the callee is required to pop its
|
|
/// own arguments. Callee pop is necessary to support tail calls.
|
|
bool isCalleePop(CallingConv::ID CallingConv,
|
|
bool is64Bit, bool IsVarArg, bool TailCallOpt);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// X86TargetLowering - X86 Implementation of the TargetLowering interface
|
|
class X86TargetLowering : public TargetLowering {
|
|
public:
|
|
explicit X86TargetLowering(X86TargetMachine &TM);
|
|
|
|
virtual unsigned getJumpTableEncoding() const;
|
|
|
|
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
|
|
|
|
virtual const MCExpr *
|
|
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
|
|
const MachineBasicBlock *MBB, unsigned uid,
|
|
MCContext &Ctx) const;
|
|
|
|
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
|
|
/// jumptable.
|
|
virtual SDValue getPICJumpTableRelocBase(SDValue Table,
|
|
SelectionDAG &DAG) const;
|
|
virtual const MCExpr *
|
|
getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
|
|
unsigned JTI, MCContext &Ctx) const;
|
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
/// that contains are placed at 16-byte boundaries while the rest are at
|
|
/// 4-byte boundaries.
|
|
virtual unsigned getByValTypeAlignment(Type *Ty) const;
|
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
/// means there isn't a need to check it against alignment requirement,
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
/// source is constant so it does not need to be loaded.
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
/// target-independent logic.
|
|
virtual EVT
|
|
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
|
MachineFunction &MF) const;
|
|
|
|
/// isSafeMemOpType - Returns true if it's safe to use load / store of the
|
|
/// specified type to expand memcpy / memset inline. This is mostly true
|
|
/// for all types except for some special cases. For example, on X86
|
|
/// targets without SSE2 f64 load / store are done with fldl / fstpl which
|
|
/// also does type conversion. Note the specified type doesn't have to be
|
|
/// legal as the hook is used before type legalization.
|
|
virtual bool isSafeMemOpType(MVT VT) const;
|
|
|
|
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
|
|
/// unaligned memory accesses. of the specified type. Returns whether it
|
|
/// is "fast" by reference in the second argument.
|
|
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
///
|
|
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
|
/// type with new values built out of custom code.
|
|
///
|
|
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG) const;
|
|
|
|
|
|
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
/// isTypeDesirableForOp - Return true if the target has native support for
|
|
/// the specified value type and it is 'desirable' to use the type for the
|
|
/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
|
|
/// instruction encodings are longer and some i16 instructions are slow.
|
|
virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
|
|
|
|
/// isTypeDesirable - Return true if the target has native support for the
|
|
/// specified value type and it is 'desirable' to use the type. e.g. On x86
|
|
/// i16 is legal, but undesirable since i16 instruction encodings are longer
|
|
/// and some i16 instructions are slow.
|
|
virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
|
|
|
|
virtual MachineBasicBlock *
|
|
EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
|
|
/// getTargetNodeName - This method returns the name of a target specific
|
|
/// DAG node.
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
|
|
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
|
|
|
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
|
/// in Mask are known to be either zero or one and return them in the
|
|
/// KnownZero/KnownOne bitsets.
|
|
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth = 0) const;
|
|
|
|
// ComputeNumSignBitsForTargetNode - Determine the number of bits in the
|
|
// operation that are sign bits.
|
|
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
|
|
unsigned Depth) const;
|
|
|
|
virtual bool
|
|
isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
|
|
|
|
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
|
|
|
|
virtual bool ExpandInlineAsm(CallInst *CI) const;
|
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
/// The operand object must already have been set up with the operand type.
|
|
virtual ConstraintWeight getSingleConstraintMatchWeight(
|
|
AsmOperandInfo &info, const char *constraint) const;
|
|
|
|
virtual const char *LowerXConstraint(EVT ConstraintVT) const;
|
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
|
/// true it means one of the asm constraint of the inline asm instruction
|
|
/// being processed is 'm'.
|
|
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const;
|
|
|
|
/// getRegForInlineAsmConstraint - Given a physical register constraint
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
/// register. This should only be used for C_Register constraints. On
|
|
/// error, this returns a register number of 0.
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT VT) const;
|
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
|
|
|
/// isLegalICmpImmediate - Return true if the specified immediate is legal
|
|
/// icmp immediate, that is the target has icmp instructions which can
|
|
/// compare a register against the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
virtual bool isLegalICmpImmediate(int64_t Imm) const;
|
|
|
|
/// isLegalAddImmediate - Return true if the specified immediate is legal
|
|
/// add immediate, that is the target has add instructions which can
|
|
/// add a register and the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
virtual bool isLegalAddImmediate(int64_t Imm) const;
|
|
|
|
/// isTruncateFree - Return true if it's free to truncate a value of
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
|
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
|
|
virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
|
|
|
|
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
|
|
|
|
/// isZExtFree - Return true if any actual instruction that defines a
|
|
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
|
|
/// register. This does not necessarily include registers defined in
|
|
/// unknown ways, such as incoming arguments, or copies from unknown
|
|
/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
|
|
/// does not necessarily apply to truncate instructions. e.g. on x86-64,
|
|
/// all instructions that define 32-bit values implicit zero-extend the
|
|
/// result out to 64 bits.
|
|
virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
|
|
virtual bool isZExtFree(EVT VT1, EVT VT2) const;
|
|
virtual bool isZExtFree(SDValue Val, EVT VT2) const;
|
|
|
|
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
|
|
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
|
|
/// expanded to FMAs when this method returns true, otherwise fmuladd is
|
|
/// expanded to fmul + fadd.
|
|
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
|
|
|
|
/// isNarrowingProfitable - Return true if it's profitable to narrow
|
|
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
|
|
/// from i32 to i8 but not from i32 to i16.
|
|
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
|
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
|
|
/// values are assumed to be legal.
|
|
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const;
|
|
|
|
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
|
|
/// used by Targets can use this to indicate if there is a suitable
|
|
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
|
|
/// pool entry.
|
|
virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const;
|
|
|
|
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
/// in order to save space and / or reduce runtime.
|
|
virtual bool ShouldShrinkFPConstant(EVT VT) const {
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
// shrink long double fp constant since fldt is very slow.
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
|
}
|
|
|
|
const X86Subtarget* getSubtarget() const {
|
|
return Subtarget;
|
|
}
|
|
|
|
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
|
|
/// computed in an SSE register, not on the X87 floating point stack.
|
|
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
|
}
|
|
|
|
/// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
|
|
/// for fptoui.
|
|
bool isTargetFTOL() const {
|
|
return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
|
|
}
|
|
|
|
/// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
|
|
/// used for fptoui to the given type.
|
|
bool isIntegerTypeFTOL(EVT VT) const {
|
|
return isTargetFTOL() && VT == MVT::i64;
|
|
}
|
|
|
|
/// createFastISel - This method returns a target specific FastISel object,
|
|
/// or null if the target does not support "fast" ISel.
|
|
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) const;
|
|
|
|
/// getStackCookieLocation - Return true if the target stores stack
|
|
/// protector cookies at a fixed offset in some non-standard address
|
|
/// space, and populates the address space and offset as
|
|
/// appropriate.
|
|
virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
|
|
|
|
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
|
|
SelectionDAG &DAG) const;
|
|
|
|
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE;
|
|
|
|
/// \brief Reset the operation actions based on target options.
|
|
virtual void resetOperationActions();
|
|
|
|
protected:
|
|
std::pair<const TargetRegisterClass*, uint8_t>
|
|
findRepresentativeClass(MVT VT) const;
|
|
|
|
private:
|
|
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const X86Subtarget *Subtarget;
|
|
const DataLayout *TD;
|
|
|
|
/// Used to store the TargetOptions so that we don't waste time resetting
|
|
/// the operation actions unless we have to.
|
|
TargetOptions TO;
|
|
|
|
/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
|
|
/// floating point ops.
|
|
/// When SSE is available, use it for f32 operations.
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
bool X86ScalarSSEf32;
|
|
bool X86ScalarSSEf64;
|
|
|
|
/// LegalFPImmediates - A list of legal fp immediates.
|
|
std::vector<APFloat> LegalFPImmediates;
|
|
|
|
/// addLegalFPImmediate - Indicate that this x86 target can instruction
|
|
/// select the specified FP immediate natively.
|
|
void addLegalFPImmediate(const APFloat& Imm) {
|
|
LegalFPImmediates.push_back(Imm);
|
|
}
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue LowerMemArgument(SDValue Chain,
|
|
CallingConv::ID CallConv,
|
|
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA, MachineFrameInfo *MFI,
|
|
unsigned i) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
|
|
// Call lowering helpers.
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
/// for tail call optimization. Targets which want to do tail call
|
|
/// optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
bool isCalleeStructRet,
|
|
bool isCallerStructRet,
|
|
Type *RetTy,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
|
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
|
|
SDValue Chain, bool IsTailCall, bool Is64Bit,
|
|
int FPDiff, SDLoc dl) const;
|
|
|
|
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
|
|
SelectionDAG &DAG) const;
|
|
|
|
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
|
bool isSigned,
|
|
bool isReplace) const;
|
|
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
|
|
int64_t Offset, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
virtual SDValue
|
|
LowerFormalArguments(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
virtual SDValue
|
|
LowerCall(CallLoweringInfo &CLI,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
|
|
|
virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
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virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
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virtual MVT
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getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
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virtual bool
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CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
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/// Utility function to emit atomic-load-arith operations (and, or, xor,
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/// nand, max, min, umax, umin). It takes the corresponding instruction to
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/// expand, the associated machine basic block, and the associated X86
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/// opcodes for reg/reg.
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MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Utility function to emit atomic-load-arith operations (and, or, xor,
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/// nand, add, sub, swap) for 64-bit operands on 32-bit target.
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MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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// Utility function to emit the low-level va_arg code for X86-64.
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MachineBasicBlock *EmitVAARG64WithCustomInserter(
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MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Utility function to emit the xmm reg save portion of va_start.
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MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
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MachineInstr *BInstr,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
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MachineBasicBlock *BB,
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bool Is64Bit) const;
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MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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SelectionDAG &DAG) const;
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/// Convert a comparison if required by the subtarget.
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SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
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};
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namespace X86 {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo);
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}
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}
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#endif // X86ISELLOWERING_H
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