Michael Kuperstein fd350586f5 [DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle. ... This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors. This fixes PR15872 and provides a partial fix for PR21711. Differential Revision: http://reviews.llvm.org/D6678 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224429 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-17 12:32:17 +00:00
..
AArch64	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
ARM	[ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes	2014-12-16 10:59:27 +00:00
CPP
Generic	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Hexagon	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.	2014-12-17 10:56:16 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
PowerPC	[PowerPC] Improve instruction selection bit-permuting operations (32-bit)	2014-12-16 05:51:41 +00:00
R600	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
X86	[DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.	2014-12-17 12:32:17 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00