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https://github.com/c64scene-ar/llvm-6502.git
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f20700ca77
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
5.1 KiB
LLVM
150 lines
5.1 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev64D8:
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;CHECK: vrev64.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
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;CHECK: test_vrev64D16:
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;CHECK: vrev64.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
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;CHECK: test_vrev64D32:
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;CHECK: vrev64.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %tmp2
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}
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define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
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;CHECK: test_vrev64Df:
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;CHECK: vrev64.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x float> %tmp2
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}
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define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev64Q8:
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;CHECK: vrev64.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev64Q16:
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;CHECK: vrev64.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
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;CHECK: test_vrev64Q32:
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;CHECK: vrev64.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %tmp2
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}
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define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
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;CHECK: test_vrev64Qf:
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;CHECK: vrev64.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x float> %tmp2
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}
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define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev32D8:
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;CHECK: vrev32.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
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;CHECK: test_vrev32D16:
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;CHECK: vrev32.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i16> %tmp2
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}
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define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev32Q8:
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;CHECK: vrev32.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev32Q16:
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;CHECK: vrev32.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i16> %tmp2
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}
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define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev16D8:
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;CHECK: vrev16.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev16Q8:
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;CHECK: vrev16.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i8> %tmp2
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}
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; Undef shuffle indices should not prevent matching to VREV:
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define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev64D8_undef:
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;CHECK: vrev64.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev32Q16_undef:
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;CHECK: vrev32.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
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ret <8 x i16> %tmp2
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}
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; A vcombine feeding a VREV should not obscure things. Radar 8597007.
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define void @test_with_vcombine(<4 x float>* %v) nounwind {
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;CHECK: test_with_vcombine:
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;CHECK-NOT: vext
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;CHECK: vrev64.32
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%tmp1 = load <4 x float>* %v, align 16
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%tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
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%tmp3 = extractelement <2 x double> %tmp2, i32 0
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%tmp4 = bitcast double %tmp3 to <2 x float>
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%tmp5 = extractelement <2 x double> %tmp2, i32 1
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%tmp6 = bitcast double %tmp5 to <2 x float>
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%tmp7 = fadd <2 x float> %tmp6, %tmp6
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%tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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store <4 x float> %tmp8, <4 x float>* %v, align 16
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ret void
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}
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