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https://github.com/c64scene-ar/llvm-6502.git
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8dd26253f5
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.0 KiB
C++
109 lines
3.0 KiB
C++
//===-- TargetMachine.cpp - General Target Information ---------------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the general parts of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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//---------------------------------------------------------------------------
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// Command-line options that tend to be useful on more than one back-end.
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//
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namespace llvm {
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bool HasDivModLibcall;
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bool AsmVerbosityDefault(false);
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}
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static cl::opt<bool>
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DataSections("fdata-sections",
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cl::desc("Emit data into separate sections"),
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cl::init(false));
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static cl::opt<bool>
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FunctionSections("ffunction-sections",
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cl::desc("Emit functions into separate sections"),
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cl::init(false));
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//---------------------------------------------------------------------------
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// TargetMachine Class
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//
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TargetMachine::TargetMachine(const Target &T,
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StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options)
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: TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
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CodeGenInfo(0), AsmInfo(0),
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MCRelaxAll(false),
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MCNoExecStack(false),
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MCSaveTempLabels(false),
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MCUseLoc(true),
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MCUseCFI(true),
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MCUseDwarfDirectory(false),
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Options(Options) {
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}
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TargetMachine::~TargetMachine() {
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delete CodeGenInfo;
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delete AsmInfo;
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}
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/// getRelocationModel - Returns the code generation relocation model. The
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/// choices are static, PIC, and dynamic-no-pic, and target default.
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Reloc::Model TargetMachine::getRelocationModel() const {
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if (!CodeGenInfo)
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return Reloc::Default;
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return CodeGenInfo->getRelocationModel();
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}
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/// getCodeModel - Returns the code model. The choices are small, kernel,
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/// medium, large, and target default.
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CodeModel::Model TargetMachine::getCodeModel() const {
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if (!CodeGenInfo)
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return CodeModel::Default;
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return CodeGenInfo->getCodeModel();
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}
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/// getOptLevel - Returns the optimization level: None, Less,
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/// Default, or Aggressive.
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CodeGenOpt::Level TargetMachine::getOptLevel() const {
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if (!CodeGenInfo)
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return CodeGenOpt::Default;
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return CodeGenInfo->getOptLevel();
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}
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bool TargetMachine::getAsmVerbosityDefault() {
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return AsmVerbosityDefault;
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}
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void TargetMachine::setAsmVerbosityDefault(bool V) {
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AsmVerbosityDefault = V;
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}
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bool TargetMachine::getFunctionSections() {
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return FunctionSections;
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}
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bool TargetMachine::getDataSections() {
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return DataSections;
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}
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void TargetMachine::setFunctionSections(bool V) {
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FunctionSections = V;
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}
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void TargetMachine::setDataSections(bool V) {
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DataSections = V;
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}
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