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36c7472106
AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207645 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
9.6 KiB
C++
222 lines
9.6 KiB
C++
//===- ARM64InstrInfo.h - ARM64 Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ARM64INSTRINFO_H
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#define LLVM_TARGET_ARM64INSTRINFO_H
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#include "ARM64.h"
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#include "ARM64RegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "ARM64GenInstrInfo.inc"
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namespace llvm {
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class ARM64Subtarget;
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class ARM64TargetMachine;
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class ARM64InstrInfo : public ARM64GenInstrInfo {
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// Reserve bits in the MachineMemOperand target hint flags, starting at 1.
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// They will be shifted into MOTargetHintStart when accessed.
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enum TargetMemOperandFlags {
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MOSuppressPair = 1
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};
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const ARM64RegisterInfo RI;
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const ARM64Subtarget &Subtarget;
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public:
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explicit ARM64InstrInfo(const ARM64Subtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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const ARM64RegisterInfo &getRegisterInfo() const { return RI; }
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const ARM64Subtarget &getSubTarget() const { return Subtarget; }
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const override;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// \brief Does this instruction set its full destination register to zero?
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bool isGPRZero(const MachineInstr *MI) const;
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/// \brief Does this instruction rename a GPR without modifying bits?
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bool isGPRCopy(const MachineInstr *MI) const;
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/// \brief Does this instruction rename an FPR without modifying bits?
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bool isFPRCopy(const MachineInstr *MI) const;
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/// Return true if this is load/store scales or extends its register offset.
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/// This refers to scaling a dynamic index as opposed to scaled immediates.
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/// MI should be a memory op that allows scaled addressing.
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bool isScaledAddr(const MachineInstr *MI) const;
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/// Return true if pairing the given load or store is hinted to be
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/// unprofitable.
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bool isLdStPairSuppressed(const MachineInstr *MI) const;
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/// Hint that pairing the given load or store is unprofitable.
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void suppressLdStPair(MachineInstr *MI) const;
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bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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unsigned &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool enableClusterLoads() const override { return true; }
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bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
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unsigned NumLoads) const override;
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bool shouldScheduleAdjacent(MachineInstr *First,
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MachineInstr *Second) const override;
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
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uint64_t Offset, const MDNode *MDPtr,
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DebugLoc DL) const;
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void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc, unsigned Opcode,
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llvm::ArrayRef<unsigned> Indices) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &,
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const SmallVectorImpl<MachineOperand> &Cond, unsigned,
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unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc DL, unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const override;
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
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/// Return true if the comparison instruction can be analyzed.
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bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction supplying the argument to
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/// the comparison into one that sets the zero bit in the flags register.
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bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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private:
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void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
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MachineBasicBlock *TBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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};
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/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
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/// plus Offset. This is intended to be used from within the prolog/epilog
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/// insertion (PEI) pass, where a virtual scratch register may be allocated
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/// if necessary, to be replaced by the scavenger at the end of PEI.
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void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
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const ARM64InstrInfo *TII,
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MachineInstr::MIFlag = MachineInstr::NoFlags,
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bool SetNZCV = false);
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/// rewriteARM64FrameIndex - Rewrite MI to access 'Offset' bytes from the
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/// FP. Return false if the offset could not be handled directly in MI, and
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/// return the left-over portion by reference.
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bool rewriteARM64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARM64InstrInfo *TII);
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/// \brief Use to report the frame offset status in isARM64FrameOffsetLegal.
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enum ARM64FrameOffsetStatus {
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ARM64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
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ARM64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
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ARM64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
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};
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/// \brief Check if the @p Offset is a valid frame offset for @p MI.
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/// The returned value reports the validity of the frame offset for @p MI.
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/// It uses the values defined by ARM64FrameOffsetStatus for that.
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/// If result == ARM64FrameOffsetCannotUpdate, @p MI cannot be updated to
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/// use an offset.eq
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/// If result & ARM64FrameOffsetIsLegal, @p Offset can completely be
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/// rewriten in @p MI.
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/// If result & ARM64FrameOffsetCanUpdate, @p Offset contains the
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/// amount that is off the limit of the legal offset.
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/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
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/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
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/// If set, @p EmittableOffset contains the amount that can be set in @p MI
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/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
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/// is a legal offset.
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int isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
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bool *OutUseUnscaledOp = nullptr,
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unsigned *OutUnscaledOp = nullptr,
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int *EmittableOffset = nullptr);
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static inline bool isUncondBranchOpcode(int Opc) { return Opc == ARM64::B; }
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static inline bool isCondBranchOpcode(int Opc) {
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switch (Opc) {
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case ARM64::Bcc:
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case ARM64::CBZW:
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case ARM64::CBZX:
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case ARM64::CBNZW:
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case ARM64::CBNZX:
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case ARM64::TBZ:
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case ARM64::TBNZ:
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return true;
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default:
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return false;
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}
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}
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static inline bool isIndirectBranchOpcode(int Opc) { return Opc == ARM64::BR; }
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} // end namespace llvm
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#endif
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