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LLVM backend for 6502
This function is a generalization of getMatchingSuperRegClass() to the symmetric case where both sides are using a sub-register index. It will find a super-register class and sub-register indexes that make this diagram commute: PreA SuperRC ----------> RCA | | | | PreB | | SubA | | | | V V RCB ----------> SubRC SubB This can be used to coalesce copies like: %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156317 91177308-0d34-0410-b5e6-96231b3b80d8 |
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README.txt |
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