mirror of
https://github.com/c64scene-ar/llvm-6502.git
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- Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
347 lines
13 KiB
TableGen
347 lines
13 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PTX instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PTXInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::CONSTANT;
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return false;
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}]>;
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def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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def store_global
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def store_local
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def store_parameter
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def store_shared
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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// Address operands
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def MEMri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegu32, i32imm);
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}
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def MEMii : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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def MEMpi : Operand<i32> {
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let PrintMethod = "printParamOperand";
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let MIOperandInfo = (ops i32imm);
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}
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//===----------------------------------------------------------------------===//
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// PTX Specific Node Definitions
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//===----------------------------------------------------------------------===//
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// PTX allow generic 3-reg shifts like shl r0, r1, r2
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def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
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def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
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def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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// Three-operand floating-point instruction template
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multiclass FLOAT3<string opcstr, SDNode opnode> {
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def rr32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, RRegf32:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
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def ri32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, f32imm:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
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def rr64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, RRegf64:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
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def ri64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, f64imm:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
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}
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, RRegu16:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
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def ri16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, i16imm:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
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def rr32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def ri32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def rr64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, RRegu64:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
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def ri64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, i64imm:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
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}
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// no %type directive, non-communtable
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multiclass INT3ntnc<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def ri : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def ir : InstPTX<(outs RRegu32:$d),
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(ins i32imm:$a, RRegu32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
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}
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multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
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def rr : InstPTX<(outs RC:$d),
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(ins MEMri:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRrr:$a))]>;
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def ri : InstPTX<(outs RC:$d),
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(ins MEMri:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRri:$a))]>;
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def ii : InstPTX<(outs RC:$d),
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(ins MEMii:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRii:$a))]>;
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}
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multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
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defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
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defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
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defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
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defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
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defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
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}
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multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
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def rr : InstPTX<(outs),
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(ins RC:$d, MEMri:$a),
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!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
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[(pat_store RC:$d, ADDRrr:$a)]>;
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def ri : InstPTX<(outs),
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(ins RC:$d, MEMri:$a),
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!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
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[(pat_store RC:$d, ADDRri:$a)]>;
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def ii : InstPTX<(outs),
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(ins RC:$d, MEMii:$a),
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!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
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[(pat_store RC:$d, ADDRii:$a)]>;
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}
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multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
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defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
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defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
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defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
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defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
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defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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///===- Floating-Point Arithmetic Instructions ----------------------------===//
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defm FADD : FLOAT3<"add", fadd>;
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defm FSUB : FLOAT3<"sub", fsub>;
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defm FMUL : FLOAT3<"mul", fmul>;
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///===- Integer Arithmetic Instructions -----------------------------------===//
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defm ADD : INT3<"add", add>;
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defm SUB : INT3<"sub", sub>;
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///===- Logic and Shift Instructions --------------------------------------===//
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defm SHL : INT3ntnc<"shl.b32", PTXshl>;
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defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
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defm SRA : INT3ntnc<"shr.s32", PTXsra>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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def MOVPREDrr
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: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
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def MOVU16rr
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: InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
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def MOVU32rr
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: InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
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def MOVU64rr
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: InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
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def MOVF32rr
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: InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
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def MOVF64rr
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: InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVPREDri
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: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
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[(set Preds:$d, imm:$a)]>;
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def MOVU16ri
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: InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
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[(set RRegu16:$d, imm:$a)]>;
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def MOVU32ri
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: InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
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[(set RRegu32:$d, imm:$a)]>;
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def MOVU164ri
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: InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
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[(set RRegu64:$d, imm:$a)]>;
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def MOVF32ri
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: InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
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[(set RRegf32:$d, fpimm:$a)]>;
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def MOVF64ri
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: InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
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[(set RRegf64:$d, fpimm:$a)]>;
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}
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// Loads
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defm LDg : PTX_LD_ALL<"ld.global", load_global>;
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defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
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defm LDl : PTX_LD_ALL<"ld.local", load_local>;
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defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
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// This is a special instruction that is manually inserted for kernel parameters
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def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
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"ld.param.u16\t$d, [$a]", []>;
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def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
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"ld.param.u32\t$d, [$a]", []>;
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def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
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"ld.param.u64\t$d, [$a]", []>;
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def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
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"ld.param.f32\t$d, [$a]", []>;
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def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
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"ld.param.f64\t$d, [$a]", []>;
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// Stores
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defm STg : PTX_ST_ALL<"st.global", store_global>;
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defm STl : PTX_ST_ALL<"st.local", store_local>;
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defm STs : PTX_ST_ALL<"st.shared", store_shared>;
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// defm STp : PTX_ST_ALL<"st.param", store_parameter>;
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// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
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// TODO: Do something with st.param if/when it is needed.
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///===- Control Flow Instructions -----------------------------------------===//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
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def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
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}
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