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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
163 lines
6.7 KiB
TableGen
163 lines
6.7 KiB
TableGen
//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips DSP ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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// ImmLeaf
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def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
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def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
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def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
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def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
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def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
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def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
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// Mips-specific dsp nodes
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def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
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class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
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def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
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def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
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def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
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def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
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def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
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def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
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// Instruction encoding.
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
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class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
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class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
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class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
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class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
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class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
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class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
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class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
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class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
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class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
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class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
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// Instruction desc.
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 1
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//===----------------------------------------------------------------------===//
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// Extr
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class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
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class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
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class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
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class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
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NoItinerary>;
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class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
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class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
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NoItinerary>;
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class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
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NoItinerary>;
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class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
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NoItinerary>;
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// Instruction defs.
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// MIPS DSP Rev 1
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def EXTP : EXTP_ENC, EXTP_DESC;
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def EXTPV : EXTPV_ENC, EXTPV_DESC;
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def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
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def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
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def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
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def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
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def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
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def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
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def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
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def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
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def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
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def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
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RegisterClass SrcRC> :
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DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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(COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
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def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
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def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
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def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
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def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
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def : DSPPat<(v2i16 (load addr:$a)),
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(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(v4i8 (load addr:$a)),
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(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
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class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
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