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ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
184 lines
6.9 KiB
C++
184 lines
6.9 KiB
C++
//===-- PrologEpilogCodeInserter.cpp - Insert Prolog & Epilog code for fn -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Insert SAVE/RESTORE instructions for the function
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//
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// Insert prolog code at the unique function entry point.
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// Insert epilog code at each function exit point.
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// InsertPrologEpilog invokes these only if the function is not compiled
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// with the leaf function optimization.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInternals.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Intrinsics.h"
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namespace llvm {
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namespace {
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struct InsertPrologEpilogCode : public MachineFunctionPass {
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const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
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bool runOnMachineFunction(MachineFunction &F) {
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if (!F.getInfo()->isCompiledAsLeafMethod()) {
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InsertPrologCode(F);
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InsertEpilogCode(F);
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}
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return false;
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}
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void InsertPrologCode(MachineFunction &F);
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void InsertEpilogCode(MachineFunction &F);
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};
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} // End anonymous namespace
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//------------------------------------------------------------------------
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// Create prolog and epilog code for procedure entry and exit
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//------------------------------------------------------------------------
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void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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{
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std::vector<MachineInstr*> mvec;
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameInfo& frameInfo = TM.getFrameInfo();
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we have to use a free register to hold the size.
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// See the comments below for the choice of this register.
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//
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unsigned staticStackSize = MF.getInfo()->getStaticStackSize();
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if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
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staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
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if (unsigned padsz = (staticStackSize %
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(unsigned) frameInfo.getStackFrameSizeAlignment()))
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staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
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int32_t C = - (int) staticStackSize;
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int SP = TM.getRegInfo().getStackPointer();
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if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
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mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
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.addMReg(SP, MOTy::Def));
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} else {
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// We have to put the stack size value into a register before SAVE.
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// Use register %g1 since it is volatile across calls. Note that the
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// local (%l) and in (%i) registers cannot be used before the SAVE!
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// Do this by creating a code sequence equivalent to:
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// SETSW -(stackSize), %g1
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int uregNum = TM.getRegInfo().getUnifiedRegNum(
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TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::g1);
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MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
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.addMReg(uregNum, MOTy::Def);
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M->setOperandHi32(0);
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mvec.push_back(M);
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M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
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.addMReg(uregNum, MOTy::Def);
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
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.addMReg(uregNum, MOTy::Def);
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %g1
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M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
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mvec.push_back(M);
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}
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// For varargs function bodies, insert instructions to copy incoming
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// register arguments for the ... list to the stack.
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// The first K=6 arguments are always received via int arg regs
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// (%i0 ... %i5 if K=6) .
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// By copying the varargs arguments to the stack, va_arg() then can
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// simply assume that all vararg arguments are in an array on the stack.
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//
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if (MF.getFunction()->getFunctionType()->isVarArg()) {
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int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
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int numArgRegs = TM.getRegInfo().getNumOfIntArgRegs();
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if (numFixedArgs < numArgRegs) {
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bool ignore;
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int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
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TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::i0);
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int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
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int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
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int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);
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int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
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for (int i=numFixedArgs; i < numArgRegs; ++i) {
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mvec.push_back(BuildMI(V9::STXi, 3).addMReg(firstArgReg+i).
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addMReg(fpReg).addSImm(nextArgOffset));
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nextArgOffset += argSize;
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}
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}
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}
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MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end());
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}
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void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
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{
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &MII = TM.getInstrInfo();
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock &MBB = *I;
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const BasicBlock &BB = *I->getBasicBlock();
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const Instruction *TermInst = (Instruction*)BB.getTerminator();
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if (TermInst->getOpcode() == Instruction::Ret)
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{
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int ZR = TM.getRegInfo().getZeroRegNum();
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MachineInstr *Restore =
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BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(TermInst);
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// Remove the NOPs in the delay slots of the return instruction
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unsigned numNOPs = 0;
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while (termMvec.back()->getOpcode() == V9::NOP)
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{
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assert( termMvec.back() == &MBB.back());
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termMvec.pop_back();
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MBB.erase(&MBB.back());
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++numNOPs;
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}
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assert(termMvec.back() == &MBB.back());
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
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// Append the epilog code to the end of the basic block.
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MBB.push_back(Restore);
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}
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}
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}
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FunctionPass *createPrologEpilogInsertionPass() {
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return new InsertPrologEpilogCode();
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}
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} // End llvm namespace
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