llvm-6502/test/CodeGen/ARM/constants.ll
Jakob Stoklund Olesen e7fdef420d Don't add CFG edges for redundant conditional branches.
IR that hasn't been through SimplifyCFG can look like this:

  br i1 %b, label %r, label %r

Make sure we don't create duplicate Machine CFG edges in this case.

Fix the machine code verifier to accept conditional branches with a
single CFG edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 21:39:52 +00:00

60 lines
1.1 KiB
LLVM

; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi -disable-cgp-branch-opts -verify-machineinstrs | FileCheck %s
define i32 @f1() {
; CHECK: f1
; CHECK: mov r0, #0
ret i32 0
}
define i32 @f2() {
; CHECK: f2
; CHECK: mov r0, #255
ret i32 255
}
define i32 @f3() {
; CHECK: f3
; CHECK: mov r0, #256
ret i32 256
}
define i32 @f4() {
; CHECK: f4
; CHECK: orr{{.*}}#256
ret i32 257
}
define i32 @f5() {
; CHECK: f5
; CHECK: mov r0, #-1073741761
ret i32 -1073741761
}
define i32 @f6() {
; CHECK: f6
; CHECK: mov r0, #1008
ret i32 1008
}
define void @f7(i32 %a) {
; CHECK: f7
; CHECK: cmp r0, #65536
%b = icmp ugt i32 %a, 65536
br i1 %b, label %r, label %r
r:
ret void
}
%t1 = type { <3 x float>, <3 x float> }
@const1 = global %t1 { <3 x float> zeroinitializer,
<3 x float> <float 1.000000e+00,
float 2.000000e+00,
float 3.000000e+00> }, align 16
; CHECK: const1
; CHECK: .zero 16
; CHECK: float 1.0
; CHECK: float 2.0
; CHECK: float 3.0
; CHECK: .zero 4