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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
7.7 KiB
C++
235 lines
7.7 KiB
C++
//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
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// instructions after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "postrapseudos"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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namespace {
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struct ExpandPostRA : public MachineFunctionPass {
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private:
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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public:
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static char ID; // Pass identification, replacement for typeid
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ExpandPostRA() : MachineFunctionPass(ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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private:
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bool LowerSubregToReg(MachineInstr *MI);
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bool LowerCopy(MachineInstr *MI);
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void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
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const TargetRegisterInfo *TRI);
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void TransferImplicitDefs(MachineInstr *MI);
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};
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} // end anonymous namespace
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char ExpandPostRA::ID = 0;
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char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
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INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
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"Post-RA pseudo instruction expansion pass", false, false)
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/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
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/// and the lowered replacement instructions immediately precede it.
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/// Mark the replacement instructions with the dead flag.
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void
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ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
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const TargetRegisterInfo *TRI) {
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for (MachineBasicBlock::iterator MII =
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prior(MachineBasicBlock::iterator(MI)); ; --MII) {
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if (MII->addRegisterDead(DstReg, TRI))
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break;
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assert(MII != MI->getParent()->begin() &&
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"copyPhysReg output doesn't reference destination register!");
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}
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}
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/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
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/// replacement instructions immediately precede it. Copy any implicit-def
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/// operands from MI to the replacement instruction.
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void
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ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
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continue;
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CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
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}
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}
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bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
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MI->getOperand(1).isImm() &&
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(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
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MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned InsReg = MI->getOperand(2).getReg();
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assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
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unsigned SubIdx = MI->getOperand(3).getImm();
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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"Insert destination must be in a physical register");
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assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
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"Inserted value must be in a physical register");
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DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
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if (DstSubReg == InsReg) {
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// No need to insert an identify copy instruction.
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// Watch out for case like this:
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// %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
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// We must leave %RAX live.
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if (DstReg != InsReg) {
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MI->setDesc(TII->get(TargetOpcode::KILL));
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MI->RemoveOperand(3); // SubIdx
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MI->RemoveOperand(1); // Imm
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DEBUG(dbgs() << "subreg: replace by: " << *MI);
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return true;
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}
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DEBUG(dbgs() << "subreg: eliminated!");
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} else {
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TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
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MI->getOperand(2).isKill());
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// Implicitly define DstReg for subsequent uses.
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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CopyMI->addRegisterDefined(DstReg);
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// Transfer the kill/dead flags, if needed.
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if (MI->getOperand(0).isDead())
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TransferDeadFlag(MI, DstSubReg, TRI);
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DEBUG(dbgs() << "subreg: " << *CopyMI);
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}
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DEBUG(dbgs() << '\n');
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MBB->erase(MI);
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return true;
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}
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bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
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MachineOperand &DstMO = MI->getOperand(0);
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MachineOperand &SrcMO = MI->getOperand(1);
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if (SrcMO.getReg() == DstMO.getReg()) {
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DEBUG(dbgs() << "identity copy: " << *MI);
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// No need to insert an identity copy instruction, but replace with a KILL
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// if liveness is changed.
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if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
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// We must make sure the super-register gets killed. Replace the
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// instruction with KILL.
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MI->setDesc(TII->get(TargetOpcode::KILL));
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DEBUG(dbgs() << "replaced by: " << *MI);
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return true;
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}
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// Vanilla identity copy.
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MI->eraseFromParent();
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return true;
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}
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DEBUG(dbgs() << "real copy: " << *MI);
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TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
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DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
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if (DstMO.isDead())
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TransferDeadFlag(MI, DstMO.getReg(), TRI);
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if (MI->getNumOperands() > 2)
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TransferImplicitDefs(MI);
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DEBUG({
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MachineBasicBlock::iterator dMI = MI;
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dbgs() << "replaced by: " << *(--dMI);
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});
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MI->eraseFromParent();
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return true;
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}
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/// runOnMachineFunction - Reduce subregister inserts and extracts to register
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/// copies.
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///
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bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "Machine Function\n"
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<< "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
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<< "********** Function: " << MF.getName() << '\n');
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TRI = MF.getTarget().getRegisterInfo();
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TII = MF.getTarget().getInstrInfo();
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bool MadeChange = false;
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me;) {
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MachineInstr *MI = mi;
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// Advance iterator here because MI may be erased.
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++mi;
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// Only expand pseudos.
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if (!MI->isPseudo())
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continue;
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// Give targets a chance to expand even standard pseudos.
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if (TII->expandPostRAPseudo(MI)) {
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MadeChange = true;
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continue;
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}
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// Expand standard pseudos.
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switch (MI->getOpcode()) {
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case TargetOpcode::SUBREG_TO_REG:
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MadeChange |= LowerSubregToReg(MI);
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break;
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case TargetOpcode::COPY:
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MadeChange |= LowerCopy(MI);
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break;
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case TargetOpcode::DBG_VALUE:
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continue;
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case TargetOpcode::INSERT_SUBREG:
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case TargetOpcode::EXTRACT_SUBREG:
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llvm_unreachable("Sub-register pseudos should have been eliminated.");
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}
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}
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}
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return MadeChange;
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}
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