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https://github.com/c64scene-ar/llvm-6502.git
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8493722975
This patch corresponds to review: http://reviews.llvm.org/D9941 It adds the various FMA instructions introduced in the version 2.07 of the ISA along with the testing for them. These are operations on single precision scalar values in VSX registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238578 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
5.8 KiB
LLVM
168 lines
5.8 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
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define void @test1sp(float %a, float %b, float %c, float %e, float* nocapture %d) #0 {
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entry:
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%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
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store float %0, float* %d, align 4
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%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
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%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
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store float %1, float* %arrayidx1, align 4
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ret void
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; CHECK-LABEL: @test1sp
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; CHECK-DAG: li [[C1:[0-9]+]], 4
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; CHECK-DAG: xsmaddmsp 3, 2, 1
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; CHECK-DAG: xsmaddasp 1, 2, 4
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; CHECK-DAG: stxsspx 3, 0, 7
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; CHECK-DAG: stxsspx 1, 7, [[C1]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test1sp
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
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; CHECK-FISL-DAG: stxsspx 0, 0, 7
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; CHECK-FISL-DAG: xsmaddasp 1, 2, 4
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4
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; CHECK-FISL-DAG: stxsspx 1, 7, [[C1]]
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; CHECK-FISL: blr
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}
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define void @test2sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
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entry:
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%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
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store float %0, float* %d, align 4
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%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
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%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
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store float %1, float* %arrayidx1, align 4
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%2 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
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%arrayidx2 = getelementptr inbounds float, float* %d, i64 2
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store float %2, float* %arrayidx2, align 4
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ret void
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; CHECK-LABEL: @test2sp
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; CHECK-DAG: li [[C1:[0-9]+]], 4
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; CHECK-DAG: li [[C2:[0-9]+]], 8
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; CHECK-DAG: xsmaddmsp 3, 2, 1
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; CHECK-DAG: xsmaddmsp 4, 2, 1
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; CHECK-DAG: xsmaddasp 1, 2, 5
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; CHECK-DAG: stxsspx 3, 0, 8
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; CHECK-DAG: stxsspx 4, 8, [[C1]]
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; CHECK-DAG: stxsspx 1, 8, [[C2]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test2sp
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
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; CHECK-FISL-DAG: stxsspx 0, 0, 8
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddasp 0, 2, 4
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4
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; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
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; CHECK-FISL: blr
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}
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define void @test3sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
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entry:
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%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
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store float %0, float* %d, align 4
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%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
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%2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)
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%arrayidx1 = getelementptr inbounds float, float* %d, i64 3
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store float %2, float* %arrayidx1, align 4
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%3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
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%arrayidx2 = getelementptr inbounds float, float* %d, i64 2
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store float %3, float* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds float, float* %d, i64 1
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store float %1, float* %arrayidx3, align 4
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ret void
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; CHECK-LABEL: @test3sp
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 12
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; CHECK-DAG: li [[C2:[0-9]+]], 8
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; CHECK-DAG: li [[C3:[0-9]+]], 4
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; CHECK-DAG: xsmaddmsp 4, 2, 1
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; CHECK-DAG: xsmaddasp 1, 2, 5
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddasp [[F1]], 2, 3
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; CHECK-DAG: xsmaddmsp 3, 2, 4
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; CHECK-DAG: stxsspx [[F1]], 0, 8
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; CHECK-DAG: stxsspx 3, 8, [[C1]]
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; CHECK-DAG: stxsspx 1, 8, [[C2]]
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; CHECK-DAG: stxsspx 4, 8, [[C3]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test3sp
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; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4
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; CHECK-FISL-DAG: fmr 4, [[F1]]
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; CHECK-FISL-DAG: xsmaddasp 4, 2, 3
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12
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; CHECK-FISL-DAG: stxsspx 4, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4
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; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]
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; CHECK-FISL: blr
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}
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define void @test4sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
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entry:
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%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
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store float %0, float* %d, align 4
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%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
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%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
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store float %1, float* %arrayidx1, align 4
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%2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)
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%arrayidx3 = getelementptr inbounds float, float* %d, i64 3
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store float %2, float* %arrayidx3, align 4
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%3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
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%arrayidx4 = getelementptr inbounds float, float* %d, i64 2
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store float %3, float* %arrayidx4, align 4
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ret void
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; CHECK-LABEL: @test4sp
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 4
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; CHECK-DAG: li [[C2:[0-9]+]], 8
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; CHECK-DAG: xsmaddmsp 4, 2, 1
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddasp 1, 2, 5
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; CHECK-DAG: xsmaddasp [[F1]], 2, 3
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; CHECK-DAG: stxsspx [[F1]], 0, 8
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; CHECK-DAG: stxsspx 4, 8, [[C1]]
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; CHECK-DAG: li [[C3:[0-9]+]], 12
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; CHECK-DAG: xsmaddasp 4, 2, 3
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; CHECK-DAG: stxsspx 4, 8, [[C3]]
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; CHECK-DAG: stxsspx 1, 8, [[C2]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test4sp
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; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 3
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; CHECK-FISL-DAG: stxsspx 0, 0, 8
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; CHECK-FISL-DAG: fmr [[F1]], 1
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; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4
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; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]
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; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12
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; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
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; CHECK-FISL: blr
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}
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declare float @llvm.fma.f32(float, float, float) #0
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