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https://github.com/c64scene-ar/llvm-6502.git
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a16c1b55e2
unrolling heuristic per default Benchmarking on x86_64 (thanks Chandler!) and ARM has shown those options speed up some benchmarks while not causing any interesting regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200621 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.7 KiB
LLVM
72 lines
2.7 KiB
LLVM
; RUN: opt < %s -loop-vectorize -mtriple=thumbv7-apple-ios3.0.0 -S | FileCheck %s
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; RUN: opt < %s -loop-vectorize -mtriple=thumbv7-apple-ios3.0.0 -mcpu=swift -S | FileCheck %s --check-prefix=SWIFT
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; RUN: opt < %s -loop-vectorize -force-vector-width=1 -mtriple=thumbv7-apple-ios3.0.0 -mcpu=swift -S | FileCheck %s --check-prefix=SWIFTUNROLL
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios3.0.0"
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;CHECK-LABEL: @foo(
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;CHECK: load <4 x i32>
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;CHECK-NOT: load <4 x i32>
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;CHECK: ret
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;SWIFT-LABEL: @foo(
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;SWIFT: load <4 x i32>
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;SWIFT: load <4 x i32>
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;SWIFT: ret
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define i32 @foo(i32* nocapture %A, i32 %n) nounwind readonly ssp {
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%1 = icmp sgt i32 %n, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph: ; preds = %0, %.lr.ph
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%i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ]
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%sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ]
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%2 = getelementptr inbounds i32* %A, i32 %i.02
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%3 = load i32* %2, align 4
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%4 = add nsw i32 %3, %sum.01
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%5 = add nsw i32 %i.02, 1
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%exitcond = icmp eq i32 %5, %n
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph, %0
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%sum.0.lcssa = phi i32 [ 0, %0 ], [ %4, %.lr.ph ]
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ret i32 %sum.0.lcssa
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}
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; Verify the register limit. On arm we don't have 16 allocatable registers.
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;SWIFTUNROLL-LABEL: @register_limit(
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;SWIFTUNROLL: load i32
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;SWIFTUNROLL-NOT: load i32
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define i32 @register_limit(i32* nocapture %A, i32 %n) {
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%1 = icmp sgt i32 %n, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph:
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%i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ]
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%sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ]
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%sum.02 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ]
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%sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ]
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%sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ]
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%sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
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%sum.06 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
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%2 = getelementptr inbounds i32* %A, i32 %i.02
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%3 = load i32* %2, align 4
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%4 = add nsw i32 %3, %sum.01
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%5 = add nsw i32 %i.02, 1
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%6 = add nsw i32 %3, %sum.02
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%7 = add nsw i32 %3, %sum.03
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%8 = add nsw i32 %3, %sum.04
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%9 = add nsw i32 %3, %sum.05
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%10 = add nsw i32 %3, %sum.05
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%exitcond = icmp eq i32 %5, %n
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph, %0
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%sum.0.lcssa = phi i32 [ 0, %0 ], [ %4, %.lr.ph ]
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%sum.1.lcssa = phi i32 [ 0, %0 ], [ %6, %.lr.ph ]
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%sum.2.lcssa = phi i32 [ 0, %0 ], [ %7, %.lr.ph ]
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%sum.4.lcssa = phi i32 [ 0, %0 ], [ %8, %.lr.ph ]
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%sum.5.lcssa = phi i32 [ 0, %0 ], [ %9, %.lr.ph ]
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%sum.6.lcssa = phi i32 [ 0, %0 ], [ %10, %.lr.ph ]
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ret i32 %sum.0.lcssa
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}
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