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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23852 91177308-0d34-0410-b5e6-96231b3b80d8
215 lines
5.0 KiB
TableGen
215 lines
5.0 KiB
TableGen
//===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//3.3:
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//Memory
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//Branch
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//Operate
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//Floating-point
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//PALcode
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def u8imm : Operand<i64>;
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def s14imm : Operand<i64>;
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def s16imm : Operand<i64>;
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def s21imm : Operand<i64>;
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def s64imm : Operand<i64>;
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline
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field bits<32> Inst;
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let Namespace = "Alpha";
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let OperandList = OL;
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let AsmString = asmstr;
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let Inst{31-26} = op;
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}
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//3.3.1
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class MForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MgForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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bits<5> Ra;
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bits<5> Rb;
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bits<14> disp;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-14} = TB;
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let Inst{13-0} = disp;
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}
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//3.3.2
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let isBranch = 1, isTerminator = 1 in
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class BForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class FBForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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//3.3.3
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class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
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let Pattern = pattern;
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bits<5> Rc;
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bits<5> Ra;
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bits<5> Rb;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
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let Pattern = pattern;
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bits<5> Rc;
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bits<5> Rb;
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bits<7> Function = fun;
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let Inst{25-21} = 0;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OForm4<bits<6> opcode, bits<7> fun, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), asmstr> {
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bits<5> Rc;
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bits<5> Rb;
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bits<5> Ra;
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bits<7> Function = fun;
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let isTwoAddress = 1;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
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let Pattern = pattern;
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bits<5> Rc;
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bits<5> Ra;
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bits<8> LIT;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-13} = LIT;
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let Inst{12} = 1;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), asmstr> {
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bits<5> Rc;
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bits<8> LIT;
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bits<5> Ra;
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bits<7> Function = fun;
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let isTwoAddress = 1;
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let Inst{25-21} = Ra;
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let Inst{20-13} = LIT;
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let Inst{12} = 1;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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//3.3.4
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class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
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: InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> {
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bits<5> Fc;
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bits<5> Fa;
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bits<5> Fb;
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bits<11> Function = fun;
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let Inst{25-21} = Fa;
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let Inst{20-16} = Fb;
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let Inst{15-5} = Function;
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let Inst{4-0} = Fc;
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}
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class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr>
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: InstAlpha<opcode, OL, asmstr> {
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bits<5> Fc;
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bits<5> Fa;
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bits<5> Fb;
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bits<11> Function = fun;
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let Inst{25-21} = Fa;
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let Inst{20-16} = Fb;
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let Inst{15-5} = Function;
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let Inst{4-0} = Fc;
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}
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//3.3.5
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class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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bits<26> Function;
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let Inst{25-0} = Function;
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}
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// Pseudo instructions.
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class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {
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}
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