mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 16:29:20 +00:00
generated by llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1882 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
8.0 KiB
Plaintext
203 lines
8.0 KiB
Plaintext
Analysing live variables ...
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For BB 0x4c6560(L1Done) :
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Defs: 0x4c65a8(recurse) 0x726cf8
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In: 0x4c6438(j3)
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Out:
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For BB 0x4c63f0(L2Done) :
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Defs: 0x4c6438(j3) 0x4d8120 0x4ddf98 0x727280(PhiCp:)
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In: 0x4d6478(i3) 0x5ab290(j2)
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Out:
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For BB 0x5ab450(L2Body) :
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Defs: 0x4d6398(i2) 0x4d6478(i3) 0x5ab498(wl) 0x726f20 0x726ff8 0x7271c0
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In: 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out:
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For BB 0x4d82a0(L1Header) :
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Defs: 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 0x727490(PhiCp:)
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out:
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For BB 0x501700(Start) :
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Defs: 0x501748(j1) 0x727280(PhiCp:)
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In:
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Out:
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After Backward Pass 0...
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For BB L1Done:
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In: 0x4c6438(j3)
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Out:
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For BB L2Done:
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In: 0x4d6478(i3) 0x5ab290(j2)
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Out: 0x4c6438(j3)
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For BB L2Body:
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In: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out: 0x4d6478(i3) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB L1Header:
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB Start:
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In: 0x5414e0(j)
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Out: 0x5414e0(j) 0x727280(PhiCp:)
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After Backward Pass 1...
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For BB L1Done:
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In: 0x4c6438(j3)
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Out:
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For BB L2Done:
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In: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
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Out: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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For BB L2Body:
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In: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB L1Header:
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB Start:
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In: 0x5414e0(j)
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Out: 0x5414e0(j) 0x727280(PhiCp:)
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Live Variable Analysis complete!
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======For BB Start: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(val j1) %reg(23) %reg(val PhiCp:)*
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Before: 0x501748(j1) 0x5414e0(j)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(23) %reg(23) %reg(val j1)*
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Before: 0x5414e0(j)
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After : 0x501748(j1) 0x5414e0(j)
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======For BB L1Header: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val j) %reg(23) %reg(val PhiCp:)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
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After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
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Live var sets before/after instruction add %reg(23) %reg(23) %reg(val i1)*
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Before: 0x5414e0(j) 0x5ab290(j2)
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After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val j2)*
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2)
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======For BB L2Body: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction nop
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction be %ccreg(val 0x726ff8) %disp(label L2Done)
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val i3) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val wl) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
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Live var sets before/after instruction subcc %reg(val i3) %reg(val 0x7271c0) %reg(23)* %ccreg(val 0x726ff8)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
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Live var sets before/after instruction setsw 10 %reg(val 0x7271c0)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
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Live var sets before/after instruction add %reg(val i2) %reg(val 0x726f20) %reg(val i3)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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Live var sets before/after instruction setsw 1 %reg(val 0x726f20)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val wl)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
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======For BB L2Done: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction nop
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction be %ccreg(val 0x4ddf98) %disp(label L1Done)
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Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(val j3) %reg(23) %reg(val PhiCp:)*
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Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
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After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction subcc %reg(val j3) %reg(val 0x4d8120) %reg(23)* %ccreg(val 0x4ddf98)*
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Before: 0x4c6438(j3) 0x4d8120 0x5414e0(j)
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After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
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Live var sets before/after instruction setsw 100 %reg(val 0x4d8120)*
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Before: 0x4c6438(j3) 0x5414e0(j)
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After : 0x4c6438(j3) 0x4d8120 0x5414e0(j)
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Live var sets before/after instruction add %reg(val j2) %reg(val i3) %reg(val j3)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
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After : 0x4c6438(j3) 0x5414e0(j)
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======For BB L1Done: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before:
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After :
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Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4c65a8
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Before: 0x4c65a8(recurse)
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After :
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Live var sets before/after instruction nop
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Before: 0x4c65a8(recurse)
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After : 0x4c65a8(recurse)
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Live var sets before/after instruction call %disp(label LoopTest) Implicit:0x4c6438 0x4c6438 0x4c65a8* 0x726cf8*
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Before: 0x4c6438(j3)
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After : 0x4c65a8(recurse)
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