mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d90e5063ca
The backend now assumes that all immediates are integers. This allows us to simplify immediate handling code, becasue we no longer need to handle fp and integer immediates differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225844 91177308-0d34-0410-b5e6-96231b3b80d8
276 lines
8.0 KiB
C++
276 lines
8.0 KiB
C++
//===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "si-fold-operands"
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using namespace llvm;
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namespace {
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class SIFoldOperands : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Fold Operands";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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struct FoldCandidate {
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MachineInstr *UseMI;
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unsigned UseOpNo;
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MachineOperand *OpToFold;
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uint64_t ImmToFold;
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FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp) :
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UseMI(MI), UseOpNo(OpNo) {
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if (FoldOp->isImm()) {
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OpToFold = nullptr;
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ImmToFold = FoldOp->getImm();
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} else {
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assert(FoldOp->isReg());
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OpToFold = FoldOp;
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}
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}
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bool isImm() const {
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return !OpToFold;
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIFoldOperands, DEBUG_TYPE,
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"SI Fold Operands", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(SIFoldOperands, DEBUG_TYPE,
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"SI Fold Operands", false, false)
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char SIFoldOperands::ID = 0;
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char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
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FunctionPass *llvm::createSIFoldOperandsPass() {
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return new SIFoldOperands();
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}
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static bool isSafeToFold(unsigned Opcode) {
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switch(Opcode) {
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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case AMDGPU::V_MOV_B64_PSEUDO:
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::COPY:
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return true;
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default:
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return false;
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}
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}
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static bool updateOperand(FoldCandidate &Fold,
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const TargetRegisterInfo &TRI) {
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MachineInstr *MI = Fold.UseMI;
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MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
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assert(Old.isReg());
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if (Fold.isImm()) {
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Old.ChangeToImmediate(Fold.ImmToFold);
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return true;
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}
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MachineOperand *New = Fold.OpToFold;
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if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&
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TargetRegisterInfo::isVirtualRegister(New->getReg())) {
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Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
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return true;
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}
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// FIXME: Handle physical registers.
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return false;
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}
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static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
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MachineInstr *MI, unsigned OpNo,
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MachineOperand *OpToFold,
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const SIInstrInfo *TII) {
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if (!TII->isOperandLegal(MI, OpNo, OpToFold)) {
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// Operand is not legal, so try to commute the instruction to
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// see if this makes it possible to fold.
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unsigned CommuteIdx0;
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unsigned CommuteIdx1;
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bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1);
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if (CanCommute) {
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if (CommuteIdx0 == OpNo)
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OpNo = CommuteIdx1;
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else if (CommuteIdx1 == OpNo)
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OpNo = CommuteIdx0;
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}
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if (!CanCommute || !TII->commuteInstruction(MI))
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return false;
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if (!TII->isOperandLegal(MI, OpNo, OpToFold))
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return false;
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}
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FoldList.push_back(FoldCandidate(MI, OpNo, OpToFold));
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return true;
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}
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bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (!isSafeToFold(MI.getOpcode()))
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continue;
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MachineOperand &OpToFold = MI.getOperand(1);
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bool FoldingImm = OpToFold.isImm();
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// FIXME: We could also be folding things like FrameIndexes and
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// TargetIndexes.
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if (!FoldingImm && !OpToFold.isReg())
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continue;
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// Folding immediates with more than one use will increase program side.
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// FIXME: This will also reduce register usage, which may be better
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// in some cases. A better heuristic is needed.
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if (FoldingImm && !TII->isInlineConstant(OpToFold) &&
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!MRI.hasOneUse(MI.getOperand(0).getReg()))
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continue;
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// FIXME: Fold operands with subregs.
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if (OpToFold.isReg() &&
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(!TargetRegisterInfo::isVirtualRegister(OpToFold.getReg()) ||
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OpToFold.getSubReg()))
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continue;
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std::vector<FoldCandidate> FoldList;
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for (MachineRegisterInfo::use_iterator
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Use = MRI.use_begin(MI.getOperand(0).getReg()), E = MRI.use_end();
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Use != E; ++Use) {
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MachineInstr *UseMI = Use->getParent();
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const MachineOperand &UseOp = UseMI->getOperand(Use.getOperandNo());
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// FIXME: Fold operands with subregs.
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if (UseOp.isReg() && UseOp.getSubReg() && OpToFold.isReg()) {
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continue;
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}
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APInt Imm;
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if (FoldingImm) {
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const TargetRegisterClass *UseRC = MRI.getRegClass(UseOp.getReg());
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Imm = APInt(64, OpToFold.getImm());
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// Split 64-bit constants into 32-bits for folding.
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if (UseOp.getSubReg()) {
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if (UseRC->getSize() != 8)
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continue;
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if (UseOp.getSubReg() == AMDGPU::sub0) {
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Imm = Imm.getLoBits(32);
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} else {
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assert(UseOp.getSubReg() == AMDGPU::sub1);
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Imm = Imm.getHiBits(32);
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}
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}
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// In order to fold immediates into copies, we need to change the
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// copy to a MOV.
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if (UseMI->getOpcode() == AMDGPU::COPY) {
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unsigned MovOp = TII->getMovOpcode(
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MRI.getRegClass(UseMI->getOperand(0).getReg()));
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if (MovOp == AMDGPU::COPY)
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continue;
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UseMI->setDesc(TII->get(MovOp));
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}
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}
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const MCInstrDesc &UseDesc = UseMI->getDesc();
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// Don't fold into target independent nodes. Target independent opcodes
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// don't have defined register classes.
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if (UseDesc.isVariadic() ||
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UseDesc.OpInfo[Use.getOperandNo()].RegClass == -1)
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continue;
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if (FoldingImm) {
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MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
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tryAddToFoldList(FoldList, UseMI, Use.getOperandNo(), &ImmOp, TII);
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continue;
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}
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tryAddToFoldList(FoldList, UseMI, Use.getOperandNo(), &OpToFold, TII);
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// FIXME: We could try to change the instruction from 64-bit to 32-bit
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// to enable more folding opportunites. The shrink operands pass
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// already does this.
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}
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for (FoldCandidate &Fold : FoldList) {
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if (updateOperand(Fold, TRI)) {
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// Clear kill flags.
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if (!Fold.isImm()) {
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assert(Fold.OpToFold && Fold.OpToFold->isReg());
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Fold.OpToFold->setIsKill(false);
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}
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DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " <<
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Fold.UseOpNo << " of " << *Fold.UseMI << '\n');
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}
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}
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}
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}
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return false;
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}
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