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40a5a1b39e
trip counts in more cases. Generalize ScalarEvolution's isLoopGuardedByCond code to recognize And and Or conditions, splitting the code out into an isNecessaryCond helper function so that it can evaluate Ands and Ors recursively, and make SCEVExpander be much more aggressive about hoisting instructions out of loops. test/CodeGen/X86/pr3495.ll has an additional instruction now, but it appears to be due to an arbitrary register allocation difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74048 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
3.3 KiB
LLVM
81 lines
3.3 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of reloads omited} | grep 2
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; RUN: llvm-as < %s | llc -march=x86 -stats |& not grep {Number of available reloads turned into copies}
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; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of machine instrs printed} | grep 39
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; PR3495
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; The loop reversal kicks in once here, resulting in one fewer instruction.
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target triple = "i386-pc-linux-gnu"
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@x = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=1]
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@rows = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=2]
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@up = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=2]
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@down = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=1]
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define i32 @queens(i32 %c) nounwind {
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entry:
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%tmp91 = add i32 %c, 1 ; <i32> [#uses=3]
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%tmp135 = getelementptr [8 x i32]* @x, i32 0, i32 %tmp91 ; <i32*> [#uses=1]
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br label %bb
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bb: ; preds = %bb569, %entry
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%r25.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %indvar.next715, %bb569 ] ; <i32> [#uses=4]
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%tmp27 = getelementptr [8 x i32]* @rows, i32 0, i32 %r25.0.reg2mem.0 ; <i32*> [#uses=1]
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%tmp28 = load i32* %tmp27, align 4 ; <i32> [#uses=1]
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%tmp29 = icmp eq i32 %tmp28, 0 ; <i1> [#uses=1]
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br i1 %tmp29, label %bb569, label %bb31
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bb31: ; preds = %bb
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%tmp35 = sub i32 %r25.0.reg2mem.0, 0 ; <i32> [#uses=1]
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%tmp36 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp35 ; <i32*> [#uses=1]
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%tmp37 = load i32* %tmp36, align 4 ; <i32> [#uses=1]
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%tmp38 = icmp eq i32 %tmp37, 0 ; <i1> [#uses=1]
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br i1 %tmp38, label %bb569, label %bb41
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bb41: ; preds = %bb31
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%tmp54 = sub i32 %r25.0.reg2mem.0, %c ; <i32> [#uses=1]
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%tmp55 = add i32 %tmp54, 7 ; <i32> [#uses=1]
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%tmp62 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp55 ; <i32*> [#uses=2]
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store i32 0, i32* %tmp62, align 4
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br label %bb92
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bb92: ; preds = %bb545, %bb41
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%r20.0.reg2mem.0 = phi i32 [ 0, %bb41 ], [ %indvar.next711, %bb545 ] ; <i32> [#uses=5]
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%tmp94 = getelementptr [8 x i32]* @rows, i32 0, i32 %r20.0.reg2mem.0 ; <i32*> [#uses=1]
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%tmp95 = load i32* %tmp94, align 4 ; <i32> [#uses=0]
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%tmp112 = add i32 %r20.0.reg2mem.0, %tmp91 ; <i32> [#uses=1]
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%tmp113 = getelementptr [15 x i32]* @down, i32 0, i32 %tmp112 ; <i32*> [#uses=2]
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%tmp114 = load i32* %tmp113, align 4 ; <i32> [#uses=1]
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%tmp115 = icmp eq i32 %tmp114, 0 ; <i1> [#uses=1]
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br i1 %tmp115, label %bb545, label %bb118
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bb118: ; preds = %bb92
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%tmp122 = sub i32 %r20.0.reg2mem.0, %tmp91 ; <i32> [#uses=0]
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store i32 0, i32* %tmp113, align 4
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store i32 %r20.0.reg2mem.0, i32* %tmp135, align 4
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br label %bb142
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bb142: ; preds = %bb142, %bb118
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%k18.0.reg2mem.0 = phi i32 [ 0, %bb118 ], [ %indvar.next709, %bb142 ] ; <i32> [#uses=1]
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%indvar.next709 = add i32 %k18.0.reg2mem.0, 1 ; <i32> [#uses=2]
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%exitcond710 = icmp eq i32 %indvar.next709, 8 ; <i1> [#uses=1]
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br i1 %exitcond710, label %bb155, label %bb142
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bb155: ; preds = %bb142
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%tmp156 = tail call i32 @putchar(i32 10) nounwind ; <i32> [#uses=0]
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br label %bb545
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bb545: ; preds = %bb155, %bb92
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%indvar.next711 = add i32 %r20.0.reg2mem.0, 1 ; <i32> [#uses=2]
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%exitcond712 = icmp eq i32 %indvar.next711, 8 ; <i1> [#uses=1]
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br i1 %exitcond712, label %bb553, label %bb92
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bb553: ; preds = %bb545
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store i32 1, i32* %tmp62, align 4
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br label %bb569
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bb569: ; preds = %bb553, %bb31, %bb
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%indvar.next715 = add i32 %r25.0.reg2mem.0, 1 ; <i32> [#uses=1]
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br label %bb
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}
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declare i32 @putchar(i32)
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