llvm-6502/test/CodeGen
Evan Cheng ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 18:35:56 +00:00
..
Alpha Make promotion in operation legalization for SETCC work correctly. 2009-07-17 05:16:04 +00:00
ARM Add VFP3 D registers to the DPR register class. 2009-07-29 23:03:41 +00:00
CBackend Fix an erroneous check for isFNeg; the FNeg case is handled 2009-06-04 23:43:29 +00:00
CellSPU Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 2009-06-16 06:58:29 +00:00
CPP
Generic Remove the IA-64 backend. 2009-07-24 00:30:09 +00:00
Mips Remove SectionKind::Small*. This was only used on mips, and is apparently 2009-07-24 03:11:51 +00:00
MSP430
PIC16 Test case to check that separate section is created for a global variable specified with section attribute. 2009-07-27 16:20:41 +00:00
PowerPC Revert r75663 (and r76805), as it is causing regressions on powerpc. 2009-07-23 00:09:46 +00:00
SPARC
SystemZ convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin" 2009-07-21 17:36:24 +00:00
Thumb tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 2009-07-28 07:38:35 +00:00
Thumb2 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 2009-07-31 18:35:56 +00:00
X86 fix PR4650: we only track sizes for certain objects, so only put something 2009-07-31 16:17:13 +00:00
XCore Add tests for handling of globals and tls on the XCore. These currently fail 2009-07-24 00:38:20 +00:00