Matt Arsenault ff71812dfa Fix CodeGen for different size address space GEPs ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193111 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-21 20:03:54 +00:00
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AArch64	[AArch64] Add support for NEON scalar extract narrow instructions.	2013-10-18 14:03:24 +00:00
ARM	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
CPP
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon
Inputs
Mips	[mips][msa] Fix definition of SLD instruction.	2013-10-21 11:47:56 +00:00
MSP430	Fix MSP430 calling convention to match MSPGCC	2013-10-15 08:19:39 +00:00
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC	Update PPC loop tests after SCEV non-unit-stride checkin r193015.	2013-10-19 00:14:04 +00:00
R600	Fix CodeGen for different size address space GEPs	2013-10-21 20:03:54 +00:00
SPARC	[Sparc] Disable tail call optimization for sparc64.	2013-10-09 12:50:39 +00:00
SystemZ	Replace sra with srl if a single sign bit is required	2013-10-17 11:16:57 +00:00
Thumb	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
Thumb2	MachineSink: Fix and tweak critical-edge breaking heuristic.	2013-10-14 16:57:17 +00:00
X86	X86 vector element shift-by-immediate instructions take i8 immediates. Make	2013-10-21 17:51:24 +00:00
XCore	XCore target fix bug in emitArrayBound() causing segmentation fault	2013-10-11 10:27:13 +00:00