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https://github.com/c64scene-ar/llvm-6502.git
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6035518e3b
shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
3.0 KiB
C++
82 lines
3.0 KiB
C++
//=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXFrameLowering.h"
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXSubtarget.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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NVPTXFrameLowering::NVPTXFrameLowering(NVPTXSubtarget &STI)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0),
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is64bit(STI.is64Bit()) {}
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bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
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void NVPTXFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (MF.getFrameInfo()->hasStackObjects()) {
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MachineBasicBlock &MBB = MF.front();
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// Insert "mov.u32 %SP, %Depot"
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// This instruction really occurs before first instruction
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// in the BB, so giving it no debug location.
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DebugLoc dl = DebugLoc();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// mov %SPL, %depot;
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// cvta.local %SP, %SPL;
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if (is64bit) {
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unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
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MachineInstr *MI =
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BuildMI(MBB, MBBI, dl, MF.getSubtarget().getInstrInfo()->get(
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NVPTX::cvta_local_yes_64),
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NVPTX::VRFrame).addReg(LocalReg);
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BuildMI(MBB, MI, dl,
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MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64),
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LocalReg).addImm(MF.getFunctionNumber());
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} else {
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unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
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MachineInstr *MI =
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BuildMI(MBB, MBBI, dl,
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MF.getSubtarget().getInstrInfo()->get(NVPTX::cvta_local_yes),
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NVPTX::VRFrame).addReg(LocalReg);
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BuildMI(MBB, MI, dl,
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MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR),
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LocalReg).addImm(MF.getFunctionNumber());
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}
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}
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}
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void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {}
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// This function eliminates ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void NVPTXFrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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