llvm-6502

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History

Duncan Sands 667d4b8de6 Introduce new linkage types linkonce_odr, weak_odr, common_odr and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an equivalent global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8		2009-03-07 15:45:40 +00:00
..
AsmPrinter	Introduce new linkage types linkonce_odr, weak_odr, common_odr	2009-03-07 15:45:40 +00:00
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp	Add explicit keywords.	2009-02-18 16:37:45 +00:00
Makefile
README.txt
Sparc.h	Overhaul my earlier submission due to feedback. It's a large patch, but most of	2009-02-24 08:30:20 +00:00
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp	Factor out the code to add a MachineOperand to a MachineInstrBuilder.	2009-02-18 05:45:50 +00:00
SparcInstrInfo.h
SparcInstrInfo.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp
SparcISelLowering.h
SparcRegisterInfo.cpp	Propagate debug loc info through prologue/epilogue.	2009-02-23 00:42:30 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp
SparcTargetAsmInfo.h
SparcTargetMachine.cpp	Overhaul my earlier submission due to feedback. It's a large patch, but most of	2009-02-24 08:30:20 +00:00
SparcTargetMachine.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots