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https://github.com/c64scene-ar/llvm-6502.git
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03c060b6d4
Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: echristo, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239464 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
3.3 KiB
C++
105 lines
3.3 KiB
C++
//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides PowerPC specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
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#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/MathExtras.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class Target;
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class Triple;
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class StringRef;
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class raw_pwrite_stream;
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class raw_ostream;
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extern Target ThePPC32Target;
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extern Target ThePPC64Target;
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extern Target ThePPC64LETarget;
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MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU);
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/// Construct an PPC ELF object writer.
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MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
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bool IsLittleEndian, uint8_t OSABI);
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/// Construct a PPC Mach-O object writer.
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MCObjectWriter *createPPCMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
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uint32_t CPUType,
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uint32_t CPUSubtype);
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/// Returns true iff Val consists of one contiguous run of 1s with any number of
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/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
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/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
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/// since all 1s are not contiguous.
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static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (!Val)
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return false;
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = countLeadingZeros(Val);
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// look for the first zero bit after the run of ones
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ME = countLeadingZeros((Val - 1) ^ Val);
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return true;
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} else {
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Val = ~Val; // invert mask
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if (isShiftedMask_32(Val)) {
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// effectively look for the first zero bit
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ME = countLeadingZeros(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = countLeadingZeros((Val - 1) ^ Val) + 1;
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return true;
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}
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}
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// no run present
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return false;
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}
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} // End llvm namespace
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// Generated files will use "namespace PPC". To avoid symbol clash,
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// undefine PPC here. PPC may be predefined on some hosts.
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#undef PPC
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// Defines symbolic names for PowerPC registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "PPCGenRegisterInfo.inc"
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// Defines symbolic names for the PowerPC instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "PPCGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "PPCGenSubtargetInfo.inc"
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#endif
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