Craig Topper a996db696b [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224862 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-26 18:20:05 +00:00
..
avx-512.txt	AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction	2014-10-26 09:52:24 +00:00
fp-stack.txt
hex-immediates.txt	llvm-mc: Add option for prefering hex format disassembly.	2014-06-11 20:26:40 +00:00
intel-syntax-32.txt
intel-syntax.txt
invalid-VEX-vvvv.txt
lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
marked-up.txt
missing-sib.txt	Test case for r204305.	2014-03-20 06:45:10 +00:00
moffs.txt	llvm-mc: Add option for prefering hex format disassembly.	2014-06-11 20:26:40 +00:00
padlock.txt	Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.	2014-02-19 05:34:21 +00:00
prefixes.txt	[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them.	2014-12-26 18:20:05 +00:00
simple-tests.txt
truncated-input.txt
x86-16.txt
x86-32.txt	Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4.	2014-12-26 06:36:28 +00:00
x86-64.txt