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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
5.2 KiB
C++
102 lines
5.2 KiB
C++
//====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 SSE instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB;
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def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB;
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def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
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"movaps {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE1]>, TB;
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def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB, OpSize;
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def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
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"movapd {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE2]>, TB, OpSize;
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// Logical
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fand V4F32:$src1, V4F32:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fand V2F64:$src1, V2F64:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ORPSrr : I<0x56, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"orps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ORPDrr : I<0x56, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrr : I<0x57, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fxor V4F32:$src1, V4F32:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrr : I<0x57, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fxor V2F64:$src1, V2F64:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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}
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def ANDPSrm : I<0x54, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fand V4F32:$src1,
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(X86loadpv4f32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def ANDPDrm : I<0x54, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fand V2F64:$src1,
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(X86loadpv2f64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ORPSrm : I<0x56, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"orps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ORPDrm : I<0x56, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrm : I<0x57, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fxor V4F32:$src1,
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(X86loadpv4f32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrm : I<0x57, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fxor V2F64:$src1,
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(X86loadpv2f64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPSrm : I<0x55, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPDrm : I<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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}
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