mirror of
https://github.com/c64scene-ar/llvm-6502.git
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55ad1f22b4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74385 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
4.6 KiB
C++
145 lines
4.6 KiB
C++
//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMREGISTERINFO_H
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#define ARMREGISTERINFO_H
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#include "ARM.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "ARMGenRegisterInfo.h.inc"
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namespace llvm {
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class ARMSubtarget;
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class TargetInstrInfo;
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class Type;
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/// Register allocation hints.
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namespace ARMRI {
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enum {
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RegPairOdd = 1,
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RegPairEven = 2
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};
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}
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/// isARMLowRegister - Returns true if the register is low register r0-r7.
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///
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static inline bool isARMLowRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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const TargetInstrInfo &TII;
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const ARMSubtarget &STI;
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/// FramePtr - ARM physical register used as frame ptr.
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unsigned FramePtr;
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public:
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ARMBaseRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Same as previous getRegisterNumbering except it returns true in isSPVFP
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/// if the register is a single precision VFP register.
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static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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const TargetRegisterClass *getPointerRegClass() const;
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std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
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getAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const;
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unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const;
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void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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bool isLowRegister(unsigned Reg) const;
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private:
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unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
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unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
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};
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struct ARMRegisterInfo : public ARMBaseRegisterInfo {
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public:
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ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo *TII, DebugLoc dl,
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unsigned DestReg, int Val,
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ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0) const;
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/// Code Generation virtual methods...
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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};
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} // end namespace llvm
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#endif
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