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This commit a 3rd attempt at comitting the initial MIR serialization patch. The first commit (r237708) was reverted in 237730. Then the second commit (r237954) was reverted in r238007, as the MIR library under CodeGen caused a circular dependency where the CodeGen library depended on MIR and MIR library depended on CodeGen. This commit has fixed the dependencies between CodeGen and MIR by reorganizing the MIR serialization code - the code that prints out MIR has been moved to CodeGen, and the MIR library has been renamed to MIRParser. Now the CodeGen library doesn't depend on the MIRParser library, thus the circular dependency no longer exists. --Original Commit Message-- MIR Serialization: print and parse LLVM IR using MIR format. This commit is the initial commit for the MIR serialization project. It creates a new library under CodeGen called 'MIR'. This new library adds a new machine function pass that prints out the LLVM IR using the MIR format. This pass is then added as a last pass when a 'stop-after' option is used in llc. The new library adds the initial functionality for parsing of MIR files as well. This commit also extends the llc tool so that it can recognize and parse MIR input files. Reviewers: Duncan P. N. Exon Smith, Matthias Braun, Philip Reames Differential Revision: http://reviews.llvm.org/D9616 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238341 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
9.7 KiB
C++
265 lines
9.7 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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static cl::opt<cl::boolOrDefault>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the \"fast\" instruction selector"));
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void LLVMTargetMachine::initAsmInfo() {
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MRI = TheTarget.createMCRegInfo(getTargetTriple());
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MII = TheTarget.createMCInstrInfo();
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// FIXME: Having an MCSubtargetInfo on the target machine is a hack due
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// to some backends having subtarget feature dependent module level
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// code generation. This is similar to the hack in the AsmPrinter for
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// module level assembly etc.
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STI = TheTarget.createMCSubtargetInfo(getTargetTriple(), getTargetCPU(),
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getTargetFeatureString());
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MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*MRI, getTargetTriple());
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// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
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// and if the old one gets included then MCAsmInfo will be NULL and
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// we'll crash later.
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// Provide the user with a useful error message about what's wrong.
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assert(TmpAsmInfo && "MCAsmInfo not initialized. "
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"Make sure you include the correct TargetSelect.h"
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"and that InitializeAllTargetMCs() is being invoked!");
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if (Options.DisableIntegratedAS)
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TmpAsmInfo->setUseIntegratedAssembler(false);
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if (Options.CompressDebugSections)
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TmpAsmInfo->setCompressDebugSections(true);
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AsmInfo = TmpAsmInfo;
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}
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LLVMTargetMachine::LLVMTargetMachine(const Target &T,
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StringRef DataLayoutString,
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StringRef Triple, StringRef CPU,
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StringRef FS, TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: TargetMachine(T, DataLayoutString, Triple, CPU, FS, Options) {
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CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
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}
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TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](Function &F) {
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return TargetTransformInfo(BasicTTIImpl(this, F));
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});
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}
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/// addPassesToX helper drives creation and initialization of TargetPassConfig.
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static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
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PassManagerBase &PM,
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bool DisableVerify,
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AnalysisID StartAfter,
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AnalysisID StopAfter) {
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// Add internal analysis passes from the target machine.
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PM.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
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// Targets may override createPassConfig to provide a target-specific
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// subclass.
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TargetPassConfig *PassConfig = TM->createPassConfig(PM);
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PassConfig->setStartStopPasses(StartAfter, StopAfter);
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// Set PassConfig options provided by TargetMachine.
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PassConfig->setDisableVerify(DisableVerify);
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PM.add(PassConfig);
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PassConfig->addIRPasses();
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PassConfig->addCodeGenPrepare();
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PassConfig->addPassesToHandleExceptions();
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PassConfig->addISelPrepare();
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// Install a MachineModuleInfo class, which is an immutable pass that holds
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// all the per-module stuff we're generating, including MCContext.
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MachineModuleInfo *MMI = new MachineModuleInfo(
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*TM->getMCAsmInfo(), *TM->getMCRegisterInfo(), TM->getObjFileLowering());
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PM.add(MMI);
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// Set up a MachineFunction for the rest of CodeGen to work on.
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PM.add(new MachineFunctionAnalysis(*TM));
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// Enable FastISel with -fast, but allow that to be overridden.
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if (EnableFastISelOption == cl::BOU_TRUE ||
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(TM->getOptLevel() == CodeGenOpt::None &&
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EnableFastISelOption != cl::BOU_FALSE))
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TM->setFastISel(true);
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// Ask the target for an isel.
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if (PassConfig->addInstSelector())
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return nullptr;
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PassConfig->addMachinePasses();
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PassConfig->setInitialized();
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return &MMI->getContext();
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}
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bool LLVMTargetMachine::addPassesToEmitFile(
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PassManagerBase &PM, raw_pwrite_stream &Out, CodeGenFileType FileType,
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bool DisableVerify, AnalysisID StartAfter, AnalysisID StopAfter) {
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// Add common CodeGen passes.
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MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify,
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StartAfter, StopAfter);
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if (!Context)
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return true;
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if (StopAfter) {
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PM.add(createPrintMIRPass(outs()));
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return false;
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}
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if (Options.MCOptions.MCSaveTempLabels)
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Context->setAllowTemporaryLabels(false);
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const MCSubtargetInfo &STI = *getMCSubtargetInfo();
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const MCAsmInfo &MAI = *getMCAsmInfo();
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const MCRegisterInfo &MRI = *getMCRegisterInfo();
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const MCInstrInfo &MII = *getMCInstrInfo();
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std::unique_ptr<MCStreamer> AsmStreamer;
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switch (FileType) {
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case CGFT_AssemblyFile: {
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MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
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Triple(getTargetTriple()), MAI.getAssemblerDialect(), MAI, MII, MRI);
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// Create a code emitter if asked to show the encoding.
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MCCodeEmitter *MCE = nullptr;
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if (Options.MCOptions.ShowMCEncoding)
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MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
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MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
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TargetCPU);
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auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
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MCStreamer *S = getTarget().createAsmStreamer(
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*Context, std::move(FOut), Options.MCOptions.AsmVerbose,
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Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB,
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Options.MCOptions.ShowMCInst);
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AsmStreamer.reset(S);
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break;
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}
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case CGFT_ObjectFile: {
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// Create the code emitter for the target if it exists. If not, .o file
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// emission fails.
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MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
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MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
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TargetCPU);
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if (!MCE || !MAB)
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return true;
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// Don't waste memory on names of temp labels.
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Context->setUseNamesOnTempLabels(false);
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Triple T(getTargetTriple());
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AsmStreamer.reset(getTarget().createMCObjectStreamer(
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T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
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/*DWARFMustBeAtTheEnd*/ true));
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break;
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}
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case CGFT_Null:
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// The Null output is intended for use for performance analysis and testing,
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// not real users.
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AsmStreamer.reset(getTarget().createNullStreamer(*Context));
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break;
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}
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// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
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FunctionPass *Printer =
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getTarget().createAsmPrinter(*this, std::move(AsmStreamer));
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if (!Printer)
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return true;
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PM.add(Printer);
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return false;
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}
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/// addPassesToEmitMC - Add passes to the specified pass manager to get
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/// machine code emitted with the MCJIT. This method returns true if machine
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/// code is not supported. It fills the MCContext Ctx pointer which can be
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/// used to build custom MCStreamer.
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///
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bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
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raw_pwrite_stream &Out,
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bool DisableVerify) {
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// Add common CodeGen passes.
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Ctx = addPassesToGenerateCode(this, PM, DisableVerify, nullptr, nullptr);
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if (!Ctx)
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return true;
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if (Options.MCOptions.MCSaveTempLabels)
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Ctx->setAllowTemporaryLabels(false);
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// Create the code emitter for the target if it exists. If not, .o file
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// emission fails.
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const MCRegisterInfo &MRI = *getMCRegisterInfo();
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MCCodeEmitter *MCE =
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getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
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MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
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TargetCPU);
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if (!MCE || !MAB)
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return true;
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Triple T(getTargetTriple());
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const MCSubtargetInfo &STI = *getMCSubtargetInfo();
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std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
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T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
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/*DWARFMustBeAtTheEnd*/ true));
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// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
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FunctionPass *Printer =
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getTarget().createAsmPrinter(*this, std::move(AsmStreamer));
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if (!Printer)
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return true;
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PM.add(Printer);
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return false; // success!
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}
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