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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70711 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.1 KiB
TableGen
68 lines
2.1 KiB
TableGen
//===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MSP430 register file
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//===----------------------------------------------------------------------===//
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class MSP430Reg<bits<4> num, string n> : Register<n> {
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field bits<4> Num = num;
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let Namespace = "MSP430";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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def PC : MSP430Reg<0, "r0">;
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def SP : MSP430Reg<1, "r1">;
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def SR : MSP430Reg<2, "r2">;
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def CG : MSP430Reg<3, "r3">;
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def FP : MSP430Reg<4, "r4">;
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def R5 : MSP430Reg<5, "r5">;
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def R6 : MSP430Reg<6, "r6">;
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def R7 : MSP430Reg<7, "r7">;
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def R8 : MSP430Reg<8, "r8">;
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def R9 : MSP430Reg<9, "r9">;
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def R10 : MSP430Reg<10, "r10">;
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def R11 : MSP430Reg<11, "r11">;
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def R12 : MSP430Reg<12, "r12">;
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def R13 : MSP430Reg<13, "r13">;
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def R14 : MSP430Reg<14, "r14">;
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def R15 : MSP430Reg<15, "r15">;
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// FIXME: we need subregs & special handling for 8 bit stuff
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def GR16 : RegisterClass<"MSP430", [i16], 16,
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// Volatile registers
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[R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
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// Frame pointer, sometimes allocable
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FP,
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// Volatile, but not allocable
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PC, SP, SR, CG]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GR16Class::iterator
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GR16Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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// Depending on whether the function uses frame pointer or not, last 5 or 4
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// registers on the list above are reserved
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if (RI->hasFP(MF))
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return end()-5;
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else
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return end()-4;
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}
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}];
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}
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