mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29cab5f0ee
frame index. eliminateFrameIndex will replace these instructions with (LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use. This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame pointer elimination. However since they were marked as implicitly using SP they could not be rematerialised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
992 lines
34 KiB
TableGen
992 lines
34 KiB
TableGen
//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the XCore instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// Uses of CP, DP are not currently reflected in the patterns, since
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// having a physical register as an operand prevents loop hoisting and
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// since the value of these registers never changes during the life of the
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// function.
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//===----------------------------------------------------------------------===//
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// Instruction format superclass.
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//===----------------------------------------------------------------------===//
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include "XCoreInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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// HasXS1A - This predicate is true when the target processor supports XS1A
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// instructions.
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def HasXS1A : Predicate<"Subtarget.isXS1A()">;
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// HasXS1B - This predicate is true when the target processor supports XS1B
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// instructions.
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def HasXS1B : Predicate<"Subtarget.isXS1B()">;
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//===----------------------------------------------------------------------===//
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// XCore specific DAG Nodes.
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//
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// Call
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def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SDT_XCoreAddress : SDTypeProfile<1, 1,
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[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
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[]>;
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def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
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[]>;
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def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
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[]>;
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def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
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def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
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[SDNPHasChain]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def div4_xform : SDNodeXForm<imm, [{
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// Transformation function: imm/4
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assert(N->getZExtValue() % 4 == 0);
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return getI32Imm(N->getZExtValue()/4);
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}]>;
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def msksize_xform : SDNodeXForm<imm, [{
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// Transformation function: get the size of a mask
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assert(isMask_32(N->getZExtValue()));
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// look for the first non-zero bit
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return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
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}]>;
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def neg_xform : SDNodeXForm<imm, [{
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// Transformation function: -imm
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uint32_t value = N->getZExtValue();
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return getI32Imm(-value);
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}]>;
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def div4neg_xform : SDNodeXForm<imm, [{
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// Transformation function: -imm/4
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uint32_t value = N->getZExtValue();
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assert(-value % 4 == 0);
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return getI32Imm(-value/4);
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}]>;
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def immUs4Neg : PatLeaf<(imm), [{
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uint32_t value = (uint32_t)N->getZExtValue();
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return (-value)%4 == 0 && (-value)/4 <= 11;
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}]>;
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def immUs4 : PatLeaf<(imm), [{
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uint32_t value = (uint32_t)N->getZExtValue();
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return value%4 == 0 && value/4 <= 11;
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}]>;
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def immUsNeg : PatLeaf<(imm), [{
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return -((uint32_t)N->getZExtValue()) <= 11;
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}]>;
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def immUs : PatLeaf<(imm), [{
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return (uint32_t)N->getZExtValue() <= 11;
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}]>;
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def immU6 : PatLeaf<(imm), [{
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return (uint32_t)N->getZExtValue() < (1 << 6);
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}]>;
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def immU10 : PatLeaf<(imm), [{
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return (uint32_t)N->getZExtValue() < (1 << 10);
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}]>;
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def immU16 : PatLeaf<(imm), [{
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return (uint32_t)N->getZExtValue() < (1 << 16);
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}]>;
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def immU20 : PatLeaf<(imm), [{
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return (uint32_t)N->getZExtValue() < (1 << 20);
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}]>;
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// FIXME check subtarget. Currently we check if the immediate
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// is in the common subset of legal immediate values for both
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// XS1A and XS1B.
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def immMskBitp : PatLeaf<(imm), [{
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uint32_t value = (uint32_t)N->getZExtValue();
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if (!isMask_32(value)) {
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return false;
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}
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int msksize = 32 - CountLeadingZeros_32(value);
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return (msksize >= 1 && msksize <= 8)
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|| msksize == 16
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|| msksize == 24
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|| msksize == 32;
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}]>;
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// FIXME check subtarget. Currently we check if the immediate
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// is in the common subset of legal immediate values for both
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// XS1A and XS1B.
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def immBitp : PatLeaf<(imm), [{
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uint32_t value = (uint32_t)N->getZExtValue();
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return (value >= 1 && value <= 8)
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|| value == 16
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|| value == 24
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|| value == 32;
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}]>;
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def lda16f : PatFrag<(ops node:$addr, node:$offset),
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(add node:$addr, (shl node:$offset, 1))>;
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def lda16b : PatFrag<(ops node:$addr, node:$offset),
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(sub node:$addr, (shl node:$offset, 1))>;
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def ldawf : PatFrag<(ops node:$addr, node:$offset),
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(add node:$addr, (shl node:$offset, 2))>;
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def ldawb : PatFrag<(ops node:$addr, node:$offset),
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(sub node:$addr, (shl node:$offset, 2))>;
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// Instruction operand types
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def calltarget : Operand<i32>;
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def brtarget : Operand<OtherVT>;
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def pclabel : Operand<i32>;
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// Addressing modes
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def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
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def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
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[]>;
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def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
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[]>;
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// Address operands
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def MEMii : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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// Three operand short
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multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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}
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multiclass F3R_2RUS_np<string OpcStr> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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}
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multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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class F3R<string OpcStr, SDNode OpNode> : _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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class F3R_np<string OpcStr> : _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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// Three operand long
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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}
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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// Register - U6
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// Operand register - U6
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multiclass FRU6_LRU6_branch<string OpcStr> {
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def _ru6: _FRU6<
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(outs), (ins GRRegs:$cond, brtarget:$dest),
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!strconcat(OpcStr, " $cond, $dest"),
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[]>;
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def _lru6: _FLRU6<
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(outs), (ins GRRegs:$cond, brtarget:$dest),
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!strconcat(OpcStr, " $cond, $dest"),
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[]>;
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}
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multiclass FRU6_LRU6_cp<string OpcStr> {
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def _ru6: _FRU6<
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(outs GRRegs:$dst), (ins i32imm:$a),
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!strconcat(OpcStr, " $dst, cp[$a]"),
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[]>;
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def _lru6: _FLRU6<
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(outs GRRegs:$dst), (ins i32imm:$a),
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!strconcat(OpcStr, " $dst, cp[$a]"),
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[]>;
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}
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// U6
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multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
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def _u6: _FU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(OpNode immU6:$b)]>;
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def _lu6: _FLU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(OpNode immU16:$b)]>;
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}
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multiclass FU6_LU6_np<string OpcStr> {
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def _u6: _FU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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def _lu6: _FLU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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}
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// U10
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multiclass FU10_LU10_np<string OpcStr> {
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def _u10: _FU10<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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def _lu10: _FLU10<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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}
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// Two operand short
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class F2R_np<string OpcStr> : _F2R<
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(outs GRRegs:$dst), (ins GRRegs:$b),
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!strconcat(OpcStr, " $dst, $b"),
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[]>;
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// Two operand long
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
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"${:comment} ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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"${:comment} ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
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"${:comment} LDWFI $dst, $addr",
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[(set GRRegs:$dst, (load ADDRspii:$addr))]>;
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def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
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"${:comment} LDAWFI $dst, $addr",
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[(set GRRegs:$dst, ADDRspii:$addr)]>;
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def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
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"${:comment} STWFI $src, $addr",
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[(store GRRegs:$src, ADDRspii:$addr)]>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1 in {
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def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
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(ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
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"${:comment} SELECT_CC PSEUDO!",
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[(set GRRegs:$dst,
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(select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// Three operand short
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defm ADD : F3R_2RUS<"add", add>;
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defm SUB : F3R_2RUS<"sub", sub>;
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let neverHasSideEffects = 1 in {
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defm EQ : F3R_2RUS_np<"eq">;
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def LSS_3r : F3R_np<"lss">;
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def LSU_3r : F3R_np<"lsu">;
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}
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def AND_3r : F3R<"and", and>;
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def OR_3r : F3R<"or", or>;
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let mayLoad=1 in {
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def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ldw $dst, $addr[$offset]",
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[]>;
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def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
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"ldw $dst, $addr[$offset]",
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[]>;
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def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ld16s $dst, $addr[$offset]",
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[]>;
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def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ld8u $dst, $addr[$offset]",
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[]>;
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}
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let mayStore=1 in {
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def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]",
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[]>;
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def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
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"stw $val, $addr[$offset]",
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[]>;
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}
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defm SHL : F3R_2RBITP<"shl", shl>;
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defm SHR : F3R_2RBITP<"shr", srl>;
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// TODO tsetr
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// Three operand long
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def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ldaw $dst, $addr[$offset]",
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[(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
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let neverHasSideEffects = 1 in
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def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
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(ins GRRegs:$addr, i32imm:$offset),
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"ldaw $dst, $addr[$offset]",
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[]>;
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def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
|
|
"ldaw $dst, $addr[-$offset]",
|
|
[(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
|
|
(ins GRRegs:$addr, i32imm:$offset),
|
|
"ldaw $dst, $addr[-$offset]",
|
|
[]>;
|
|
|
|
def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
|
|
"lda16 $dst, $addr[$offset]",
|
|
[(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
|
|
|
|
def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
|
|
"lda16 $dst, $addr[-$offset]",
|
|
[(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
|
|
|
|
def MUL_l3r : FL3R<"mul", mul>;
|
|
// Instructions which may trap are marked as side effecting.
|
|
let hasSideEffects = 1 in {
|
|
def DIVS_l3r : FL3R<"divs", sdiv>;
|
|
def DIVU_l3r : FL3R<"divu", udiv>;
|
|
def REMS_l3r : FL3R<"rems", srem>;
|
|
def REMU_l3r : FL3R<"remu", urem>;
|
|
}
|
|
def XOR_l3r : FL3R<"xor", xor>;
|
|
defm ASHR : FL3R_L2RBITP<"ashr", sra>;
|
|
// TODO crc32, crc8, inpw, outpw
|
|
let mayStore=1 in {
|
|
def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
|
|
"st16 $val, $addr[$offset]",
|
|
[]>;
|
|
|
|
def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
|
|
"st8 $val, $addr[$offset]",
|
|
[]>;
|
|
}
|
|
|
|
// Four operand long
|
|
let Predicates = [HasXS1B], Constraints = "$src1 = $dst1,$src2 = $dst2" in {
|
|
def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
|
|
GRRegs:$src4),
|
|
"maccu $dst1, $dst2, $src3, $src4",
|
|
[]>;
|
|
|
|
def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
|
|
GRRegs:$src4),
|
|
"maccs $dst1, $dst2, $src3, $src4",
|
|
[]>;
|
|
}
|
|
|
|
// Five operand long
|
|
|
|
let Predicates = [HasXS1B] in {
|
|
def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
|
|
"ladd $dst1, $dst2, $src1, $src2, $src3",
|
|
[]>;
|
|
|
|
def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
|
|
"lsub $dst1, $dst2, $src1, $src2, $src3",
|
|
[]>;
|
|
|
|
def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
|
|
"ldiv $dst1, $dst2, $src1, $src2, $src3",
|
|
[]>;
|
|
}
|
|
|
|
// Six operand long
|
|
|
|
def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
|
|
GRRegs:$src4),
|
|
"lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
|
|
[]>;
|
|
|
|
let Predicates = [HasXS1A] in
|
|
def MACC_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
|
|
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
|
|
GRRegs:$src4),
|
|
"macc $dst1, $dst2, $src1, $src2, $src3, $src4",
|
|
[]>;
|
|
|
|
// Register - U6
|
|
|
|
//let Uses = [DP] in ...
|
|
let neverHasSideEffects = 1, isReMaterializable = 1 in
|
|
def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
|
|
"ldaw $dst, dp[$a]",
|
|
[]>;
|
|
|
|
let isReMaterializable = 1 in
|
|
def LDAWDP_lru6: _FLRU6<
|
|
(outs GRRegs:$dst), (ins MEMii:$a),
|
|
"ldaw $dst, dp[$a]",
|
|
[(set GRRegs:$dst, ADDRdpii:$a)]>;
|
|
|
|
let mayLoad=1 in
|
|
def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
|
|
"ldw $dst, dp[$a]",
|
|
[]>;
|
|
|
|
def LDWDP_lru6: _FLRU6<
|
|
(outs GRRegs:$dst), (ins MEMii:$a),
|
|
"ldw $dst, dp[$a]",
|
|
[(set GRRegs:$dst, (load ADDRdpii:$a))]>;
|
|
|
|
let mayStore=1 in
|
|
def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
|
|
"stw $val, dp[$addr]",
|
|
[]>;
|
|
|
|
def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
|
|
"stw $val, dp[$addr]",
|
|
[(store GRRegs:$val, ADDRdpii:$addr)]>;
|
|
|
|
//let Uses = [CP] in ..
|
|
let mayLoad = 1, isReMaterializable = 1 in
|
|
defm LDWCP : FRU6_LRU6_cp<"ldw">;
|
|
|
|
let Uses = [SP] in {
|
|
let mayStore=1 in {
|
|
def STWSP_ru6 : _FRU6<
|
|
(outs), (ins GRRegs:$val, i32imm:$index),
|
|
"stw $val, sp[$index]",
|
|
[(XCoreStwsp GRRegs:$val, immU6:$index)]>;
|
|
|
|
def STWSP_lru6 : _FLRU6<
|
|
(outs), (ins GRRegs:$val, i32imm:$index),
|
|
"stw $val, sp[$index]",
|
|
[(XCoreStwsp GRRegs:$val, immU16:$index)]>;
|
|
}
|
|
|
|
let mayLoad=1 in {
|
|
def LDWSP_ru6 : _FRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldw $dst, sp[$b]",
|
|
[]>;
|
|
|
|
def LDWSP_lru6 : _FLRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldw $dst, sp[$b]",
|
|
[]>;
|
|
}
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
def LDAWSP_ru6 : _FRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldaw $dst, sp[$b]",
|
|
[]>;
|
|
|
|
def LDAWSP_lru6 : _FLRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldaw $dst, sp[$b]",
|
|
[]>;
|
|
|
|
def LDAWSP_ru6_RRegs : _FRU6<
|
|
(outs RRegs:$dst), (ins i32imm:$b),
|
|
"ldaw $dst, sp[$b]",
|
|
[]>;
|
|
|
|
def LDAWSP_lru6_RRegs : _FLRU6<
|
|
(outs RRegs:$dst), (ins i32imm:$b),
|
|
"ldaw $dst, sp[$b]",
|
|
[]>;
|
|
}
|
|
}
|
|
|
|
let isReMaterializable = 1 in {
|
|
def LDC_ru6 : _FRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldc $dst, $b",
|
|
[(set GRRegs:$dst, immU6:$b)]>;
|
|
|
|
def LDC_lru6 : _FLRU6<
|
|
(outs GRRegs:$dst), (ins i32imm:$b),
|
|
"ldc $dst, $b",
|
|
[(set GRRegs:$dst, immU16:$b)]>;
|
|
}
|
|
|
|
// Operand register - U6
|
|
// TODO setc
|
|
let isBranch = 1, isTerminator = 1 in {
|
|
defm BRFT: FRU6_LRU6_branch<"bt">;
|
|
defm BRBT: FRU6_LRU6_branch<"bt">;
|
|
defm BRFF: FRU6_LRU6_branch<"bf">;
|
|
defm BRBF: FRU6_LRU6_branch<"bf">;
|
|
}
|
|
|
|
// U6
|
|
let Defs = [SP], Uses = [SP] in {
|
|
let neverHasSideEffects = 1 in
|
|
defm EXTSP : FU6_LU6_np<"extsp">;
|
|
let mayStore = 1 in
|
|
defm ENTSP : FU6_LU6_np<"entsp">;
|
|
|
|
let isReturn = 1, isTerminator = 1, mayLoad = 1 in {
|
|
defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
|
|
}
|
|
}
|
|
|
|
// TODO extdp, kentsp, krestsp, blat, setsr
|
|
// clrsr, getsr, kalli
|
|
let isBranch = 1, isTerminator = 1 in {
|
|
def BRBU_u6 : _FU6<
|
|
(outs),
|
|
(ins brtarget:$target),
|
|
"bu $target",
|
|
[]>;
|
|
|
|
def BRBU_lu6 : _FLU6<
|
|
(outs),
|
|
(ins brtarget:$target),
|
|
"bu $target",
|
|
[]>;
|
|
|
|
def BRFU_u6 : _FU6<
|
|
(outs),
|
|
(ins brtarget:$target),
|
|
"bu $target",
|
|
[]>;
|
|
|
|
def BRFU_lu6 : _FLU6<
|
|
(outs),
|
|
(ins brtarget:$target),
|
|
"bu $target",
|
|
[]>;
|
|
}
|
|
|
|
//let Uses = [CP] in ...
|
|
let Predicates = [HasXS1B], Defs = [R11], neverHasSideEffects = 1,
|
|
isReMaterializable = 1 in
|
|
def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
|
|
"ldaw r11, cp[$a]",
|
|
[]>;
|
|
|
|
let Predicates = [HasXS1B], Defs = [R11], isReMaterializable = 1 in
|
|
def LDAWCP_lu6: _FLRU6<
|
|
(outs), (ins MEMii:$a),
|
|
"ldaw r11, cp[$a]",
|
|
[(set R11, ADDRcpii:$a)]>;
|
|
|
|
// U10
|
|
// TODO ldwcpl, blacp
|
|
|
|
let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
|
|
def LDAP_u10 : _FU10<
|
|
(outs),
|
|
(ins i32imm:$addr),
|
|
"ldap r11, $addr",
|
|
[]>;
|
|
|
|
let Defs = [R11], isReMaterializable = 1 in
|
|
def LDAP_lu10 : _FLU10<
|
|
(outs),
|
|
(ins i32imm:$addr),
|
|
"ldap r11, $addr",
|
|
[(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
|
|
|
|
let isCall=1,
|
|
// All calls clobber the the link register and the non-callee-saved registers:
|
|
Defs = [R0, R1, R2, R3, R11, LR] in {
|
|
def BL_u10 : _FU10<
|
|
(outs),
|
|
(ins calltarget:$target, variable_ops),
|
|
"bl $target",
|
|
[(XCoreBranchLink immU10:$target)]>;
|
|
|
|
def BL_lu10 : _FLU10<
|
|
(outs),
|
|
(ins calltarget:$target, variable_ops),
|
|
"bl $target",
|
|
[(XCoreBranchLink immU20:$target)]>;
|
|
}
|
|
|
|
// Two operand short
|
|
// TODO getr, getst
|
|
def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
|
|
"not $dst, $b",
|
|
[(set GRRegs:$dst, (not GRRegs:$b))]>;
|
|
|
|
def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
|
|
"neg $dst, $b",
|
|
[(set GRRegs:$dst, (ineg GRRegs:$b))]>;
|
|
|
|
// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out,
|
|
// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp,
|
|
// tsetmr, sext (reg), zext (reg)
|
|
let isTwoAddress = 1 in {
|
|
let neverHasSideEffects = 1 in
|
|
def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
|
|
"sext $dst, $src2",
|
|
[]>;
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
|
|
"zext $dst, $src2",
|
|
[]>;
|
|
|
|
def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
|
|
"andnot $dst, $src2",
|
|
[(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
|
|
}
|
|
|
|
let isReMaterializable = 1, neverHasSideEffects = 1 in
|
|
def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
|
|
"mkmsk $dst, $size",
|
|
[]>;
|
|
|
|
def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
|
|
"mkmsk $dst, $size",
|
|
[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
|
|
|
|
// Two operand long
|
|
// TODO settw, setclk, setrdy, setpsc, endin, peek,
|
|
// getd, testlcl, tinitlr, getps, setps
|
|
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
|
|
"bitrev $dst, $src",
|
|
[(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
|
|
|
|
def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
|
|
"byterev $dst, $src",
|
|
[(set GRRegs:$dst, (bswap GRRegs:$src))]>;
|
|
|
|
def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
|
|
"clz $dst, $src",
|
|
[(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
|
|
|
|
// One operand short
|
|
// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
|
|
// bru, setdp, setcp, setv, setev, kcall
|
|
// dgetreg
|
|
let isBranch=1, isIndirectBranch=1, isTerminator=1 in
|
|
def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
|
|
"bau $addr",
|
|
[(brind GRRegs:$addr)]>;
|
|
|
|
let Defs=[SP], neverHasSideEffects=1 in
|
|
def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
|
|
"set sp, $src",
|
|
[]>;
|
|
|
|
let isBarrier = 1, hasCtrlDep = 1 in
|
|
def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
|
|
"ecallt $src",
|
|
[]>;
|
|
|
|
let isBarrier = 1, hasCtrlDep = 1 in
|
|
def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
|
|
"ecallf $src",
|
|
[]>;
|
|
|
|
let isCall=1,
|
|
// All calls clobber the the link register and the non-callee-saved registers:
|
|
Defs = [R0, R1, R2, R3, R11, LR] in {
|
|
def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
|
|
"bla $addr",
|
|
[(XCoreBranchLink GRRegs:$addr)]>;
|
|
}
|
|
|
|
// Zero operand short
|
|
// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
|
|
// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
|
|
// dentsp, drestsp
|
|
|
|
let Defs = [R11] in
|
|
def GETID_0R : _F0R<(outs), (ins),
|
|
"get r11, id",
|
|
[(set R11, (int_xcore_getid))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
|
|
def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
|
|
|
|
/// sext_inreg
|
|
def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
|
|
def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
|
|
def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
|
|
|
|
/// loads
|
|
def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
|
|
(LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
|
|
|
|
def : Pat<(zextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
|
|
(LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
|
|
|
|
def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
|
|
(LDW_3r GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
|
|
(LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
|
|
def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
|
|
|
|
/// anyext
|
|
def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
|
|
(LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
|
|
def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
|
|
(LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
|
|
|
|
/// stores
|
|
def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
|
|
(ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
|
|
(ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
|
|
|
|
def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
|
|
(ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
|
|
def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
|
|
(ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
|
|
|
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def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
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(STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
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def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
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(STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
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def : Pat<(store GRRegs:$val, GRRegs:$addr),
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(STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
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/// cttz
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def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
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/// trap
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def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
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///
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/// branch patterns
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///
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// unconditional branch
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def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
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// direct match equal/notequal zero brcond
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def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
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(BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
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def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
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(BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
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def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
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(BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
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def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
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(BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
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def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
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(BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
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(BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
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(BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
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(BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
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// generic brcond pattern
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def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
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///
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/// Select patterns
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///
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// direct match equal/notequal zero select
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def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
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(SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
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def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
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(SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
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def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
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(SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
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///
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/// setcc patterns, only matched when none of the above brcond
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/// patterns match
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///
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// setcc 2 register operands
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def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
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(EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
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def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
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(EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
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def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
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(LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
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def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
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(LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
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def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
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(EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
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def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
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(EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
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def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
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(LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
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def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
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(LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
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def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
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(EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
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def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
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(EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
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// setcc reg/imm operands
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def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
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(EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
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def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
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(EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
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// misc
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def : Pat<(add GRRegs:$addr, immUs4:$offset),
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(LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
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def : Pat<(sub GRRegs:$addr, immUs4:$offset),
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(LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
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def : Pat<(and GRRegs:$val, immMskBitp:$mask),
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(ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
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(SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
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def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
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(LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
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///
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/// Some peepholes
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///
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def : Pat<(mul GRRegs:$src, 3),
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(LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
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def : Pat<(mul GRRegs:$src, 5),
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(LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
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def : Pat<(mul GRRegs:$src, -3),
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(LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
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// ashr X, 32 is equivalent to ashr X, 31 on the XCore.
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def : Pat<(sra GRRegs:$src, 31),
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(ASHR_l2rus GRRegs:$src, 32)>;
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