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https://github.com/c64scene-ar/llvm-6502.git
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8aebe9f96c
Patch by Nate Begeman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15281 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.4 KiB
C++
100 lines
2.4 KiB
C++
//===- PowerPCInstrInfo.h - PowerPC Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPCINSTRUCTIONINFO_H
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#define POWERPCINSTRUCTIONINFO_H
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#include "PowerPC.h"
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#include "PowerPCRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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namespace PPC32II {
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enum {
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ArgCountShift = 0,
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ArgCountMask = 7,
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Arg0TypeShift = 3,
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Arg1TypeShift = 8,
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Arg2TypeShift = 13,
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Arg3TypeShift = 18,
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Arg4TypeShift = 23,
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VMX = 1<<28,
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PPC64 = 1<<29,
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ArgTypeMask = 31
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};
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enum {
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None = 0,
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Gpr = 1,
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Gpr0 = 2,
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Simm16 = 3,
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Zimm16 = 4,
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PCRelimm24 = 5,
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Imm24 = 6,
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Imm5 = 7,
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PCRelimm14 = 8,
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Imm14 = 9,
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Imm2 = 10,
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Crf = 11,
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Imm3 = 12,
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Imm1 = 13,
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Fpr = 14,
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Imm4 = 15,
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Imm8 = 16,
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Disimm16 = 17,
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Disimm14 = 18,
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Spr = 19,
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Sgr = 20,
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Imm15 = 21,
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Vpr = 22
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};
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}
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class PowerPCInstrInfo : public TargetInstrInfo {
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const PowerPCRegisterInfo RI;
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public:
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PowerPCInstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const;
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static unsigned invertPPCBranchOpcode(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown PPC32 branch opcode!");
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case PPC32::BEQ: return PPC32::BNE;
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case PPC32::BNE: return PPC32::BEQ;
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case PPC32::BLT: return PPC32::BGE;
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case PPC32::BGE: return PPC32::BLT;
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case PPC32::BGT: return PPC32::BLE;
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case PPC32::BLE: return PPC32::BGT;
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}
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}
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};
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}
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#endif
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