Add some more boilerplate for the 65816.
This commit is contained in:
Jeremy Rand
parent
4b9fc0c5ac
commit
036df005af
|
|
@ -0,0 +1,125 @@
|
|||
//===-- WDC65816.h - Top-level interface for WDC65816 representation --*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the entry points for global functions defined in the LLVM
|
||||
// WDC65816 back-end.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef WDC65816_H
|
||||
#define WDC65816_H
|
||||
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
|
||||
namespace llvm {
|
||||
class FunctionPass;
|
||||
class WDC65816TargetMachine;
|
||||
class formatted_raw_ostream;
|
||||
|
||||
FunctionPass *createWDC65816ISelDag(WDC65816TargetMachine &TM);
|
||||
FunctionPass *createWDC65816DelaySlotFillerPass(TargetMachine &TM);
|
||||
|
||||
} // end namespace llvm;
|
||||
|
||||
namespace llvm {
|
||||
#if 0 // JSR_TODO - Something here?
|
||||
// Enums corresponding to Sparc condition codes, both icc's and fcc's. These
|
||||
// values must be kept in sync with the ones in the .td file.
|
||||
namespace SPCC {
|
||||
enum CondCodes {
|
||||
//ICC_A = 8 , // Always
|
||||
//ICC_N = 0 , // Never
|
||||
ICC_NE = 9 , // Not Equal
|
||||
ICC_E = 1 , // Equal
|
||||
ICC_G = 10 , // Greater
|
||||
ICC_LE = 2 , // Less or Equal
|
||||
ICC_GE = 11 , // Greater or Equal
|
||||
ICC_L = 3 , // Less
|
||||
ICC_GU = 12 , // Greater Unsigned
|
||||
ICC_LEU = 4 , // Less or Equal Unsigned
|
||||
ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
|
||||
ICC_CS = 5 , // Carry Set/Less Unsigned
|
||||
ICC_POS = 14 , // Positive
|
||||
ICC_NEG = 6 , // Negative
|
||||
ICC_VC = 15 , // Overflow Clear
|
||||
ICC_VS = 7 , // Overflow Set
|
||||
|
||||
//FCC_A = 8+16, // Always
|
||||
//FCC_N = 0+16, // Never
|
||||
FCC_U = 7+16, // Unordered
|
||||
FCC_G = 6+16, // Greater
|
||||
FCC_UG = 5+16, // Unordered or Greater
|
||||
FCC_L = 4+16, // Less
|
||||
FCC_UL = 3+16, // Unordered or Less
|
||||
FCC_LG = 2+16, // Less or Greater
|
||||
FCC_NE = 1+16, // Not Equal
|
||||
FCC_E = 9+16, // Equal
|
||||
FCC_UE = 10+16, // Unordered or Equal
|
||||
FCC_GE = 11+16, // Greater or Equal
|
||||
FCC_UGE = 12+16, // Unordered or Greater or Equal
|
||||
FCC_LE = 13+16, // Less or Equal
|
||||
FCC_ULE = 14+16, // Unordered or Less or Equal
|
||||
FCC_O = 15+16 // Ordered
|
||||
};
|
||||
}
|
||||
|
||||
inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
|
||||
switch (CC) {
|
||||
case SPCC::ICC_NE: return "ne";
|
||||
case SPCC::ICC_E: return "e";
|
||||
case SPCC::ICC_G: return "g";
|
||||
case SPCC::ICC_LE: return "le";
|
||||
case SPCC::ICC_GE: return "ge";
|
||||
case SPCC::ICC_L: return "l";
|
||||
case SPCC::ICC_GU: return "gu";
|
||||
case SPCC::ICC_LEU: return "leu";
|
||||
case SPCC::ICC_CC: return "cc";
|
||||
case SPCC::ICC_CS: return "cs";
|
||||
case SPCC::ICC_POS: return "pos";
|
||||
case SPCC::ICC_NEG: return "neg";
|
||||
case SPCC::ICC_VC: return "vc";
|
||||
case SPCC::ICC_VS: return "vs";
|
||||
case SPCC::FCC_U: return "u";
|
||||
case SPCC::FCC_G: return "g";
|
||||
case SPCC::FCC_UG: return "ug";
|
||||
case SPCC::FCC_L: return "l";
|
||||
case SPCC::FCC_UL: return "ul";
|
||||
case SPCC::FCC_LG: return "lg";
|
||||
case SPCC::FCC_NE: return "ne";
|
||||
case SPCC::FCC_E: return "e";
|
||||
case SPCC::FCC_UE: return "ue";
|
||||
case SPCC::FCC_GE: return "ge";
|
||||
case SPCC::FCC_UGE: return "uge";
|
||||
case SPCC::FCC_LE: return "le";
|
||||
case SPCC::FCC_ULE: return "ule";
|
||||
case SPCC::FCC_O: return "o";
|
||||
}
|
||||
llvm_unreachable("Invalid cond code");
|
||||
}
|
||||
|
||||
inline static unsigned HI22(int64_t imm) {
|
||||
return (unsigned)((imm >> 10) & ((1 << 22)-1));
|
||||
}
|
||||
|
||||
inline static unsigned LO10(int64_t imm) {
|
||||
return (unsigned)(imm & 0x3FF);
|
||||
}
|
||||
|
||||
inline static unsigned HIX22(int64_t imm) {
|
||||
return HI22(~imm);
|
||||
}
|
||||
|
||||
inline static unsigned LOX10(int64_t imm) {
|
||||
return ~LO10(~imm);
|
||||
}
|
||||
#endif
|
||||
|
||||
} // end namespace llvm
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
//===-- WDC65816.td - Describe the WDC65816 Target Machine -------*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Target-independent interfaces which we are implementing
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "llvm/Target/Target.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// WDC65816 Subtarget features.
|
||||
//
|
||||
|
||||
//def FeatureV9
|
||||
// : SubtargetFeature<"v9", "IsV9", "true",
|
||||
// "Enable SPARC-V9 instructions">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register File, Calling Conv, Instruction Descriptions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "WDC65816RegisterInfo.td"
|
||||
include "WDC65816CallingConv.td"
|
||||
include "WDC65816InstrInfo.td"
|
||||
|
||||
def WDC65816InstrInfo : InstrInfo;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// WDC65816 processors supported.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class Proc<string Name, list<SubtargetFeature> Features>
|
||||
: Processor<Name, NoItineraries, Features>;
|
||||
|
||||
def : Proc<"wdc65816", []>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Declare the target which we are implementing
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def WDC65816 : Target {
|
||||
// Pull in Instruction Info:
|
||||
let InstructionSet = WDC65816InstrInfo;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
//===- WDCCallingConv.td - Calling Conventions WDC65816 -----*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This describes the calling conventions for the WDC65816 architectures.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Return Value Calling Conventions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// WDC C return-value convention.
|
||||
def RetCC_WDC : CallingConv<[
|
||||
CCIfType<[i16], CCAssignToReg<[A]>>,
|
||||
CCIfType<[i32], CCAssignToReg<[X, A]>>
|
||||
]>;
|
||||
|
||||
// WDC C Calling convention.
|
||||
def CC_WDC : CallingConv<[
|
||||
CCIfType<[i8], CCAssignToStack<1, 1>>,
|
||||
CCIfType<[i16], CCAssignToStack<2, 1>>,
|
||||
CCIfType<[i32, f32], CCAssignToStack<4, 1>>
|
||||
]>;
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
//===- WDC65816RegisterInfo.td - WDC65816 Register defs ----------*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Declarations that describe the WDC65816 register file
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Namespace = "WDC" in {
|
||||
def A : Register<"A">;
|
||||
def X : Register<"X">;
|
||||
def Y : Register<"Y">;
|
||||
def P : Register<"P">;
|
||||
def S : Register<"S">;
|
||||
def D : Register<"D">;
|
||||
def K : Register<"K">;
|
||||
def B : Register<"B">;
|
||||
def PC : Register<"PC">;
|
||||
}
|
||||
|
||||
def IntRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add A, X, Y)>;
|
||||
|
||||
def AccRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add A)>;
|
||||
|
||||
def IndexRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add X, Y)>;
|
||||
|
||||
def IndexXRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add X)>;
|
||||
|
||||
def IndexYRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add Y)>;
|
||||
|
||||
def DataBankRegs : RegisterClass<"WDC", [i8], 8,
|
||||
(add B)>;
|
||||
|
||||
def DirectPageRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add D)>;
|
||||
|
||||
def StackPointerRegs : RegisterClass<"WDC", [i16], 8,
|
||||
(add S)>;
|
||||
|
||||
def ProcessorStatusRegs : RegisterClass<"WDC", [i8], 8,
|
||||
(add P)>;
|
||||
|
||||
def ProgramBankRegs : RegisterClass<"WDC", [i8], 8,
|
||||
(add K)>;
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
//===-- WDC65816TargetMachine.cpp - Define TargetMachine for WDC65816 -----------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "WDC65816TargetMachine.h"
|
||||
#include "WDC65816.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
extern "C" void LLVMInitializeWDC65816Target() {
|
||||
// Register the target.
|
||||
RegisterTargetMachine<WDC65816TargetMachine> X(TheWDC65816Target);
|
||||
}
|
||||
|
||||
/// WDC65816TargetMachine ctor
|
||||
///
|
||||
WDC65816TargetMachine::WDC65816TargetMachine(const Target &T, StringRef TT,
|
||||
StringRef CPU, StringRef FS,
|
||||
const TargetOptions &Options,
|
||||
Reloc::Model RM, CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL)
|
||||
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
|
||||
DL(Subtarget.getDataLayout()),
|
||||
InstrInfo(Subtarget),
|
||||
TLInfo(*this), TSInfo(*this),
|
||||
FrameLowering(Subtarget) {
|
||||
initAsmInfo();
|
||||
}
|
||||
|
||||
namespace {
|
||||
/// WDC65816 Code Generator Pass Configuration Options.
|
||||
class WDC65816PassConfig : public TargetPassConfig {
|
||||
public:
|
||||
WDC65816PassConfig(WDC65816TargetMachine *TM, PassManagerBase &PM)
|
||||
: TargetPassConfig(TM, PM) {}
|
||||
|
||||
WDC65816TargetMachine &getWDC65816TargetMachine() const {
|
||||
return getTM<WDC65816TargetMachine>();
|
||||
}
|
||||
|
||||
virtual bool addInstSelector();
|
||||
virtual bool addPreEmitPass();
|
||||
};
|
||||
} // namespace
|
||||
|
||||
TargetPassConfig *WDC65816TargetMachine::createPassConfig(PassManagerBase &PM) {
|
||||
return new WDC65816PassConfig(this, PM);
|
||||
}
|
||||
|
||||
bool WDC65816PassConfig::addInstSelector() {
|
||||
addPass(createWDC65816ISelDag(getWDC65816TargetMachine()));
|
||||
return false;
|
||||
}
|
||||
|
||||
/// addPreEmitPass - This pass may be implemented by targets that want to run
|
||||
/// passes immediately before machine code is emitted. This should return
|
||||
/// true if -print-machineinstrs should print out the code after the passes.
|
||||
bool WDC65816PassConfig::addPreEmitPass(){
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
//===-- WDC65816TargetMachine.h - Define TargetMachine for WDC65816 ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file declares the Sparc specific subclass of TargetMachine.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef WDC65816TARGETMACHINE_H
|
||||
#define WDC65816TARGETMACHINE_H
|
||||
|
||||
#include "WDC65816FrameLowering.h"
|
||||
#include "WDC65816ISelLowering.h"
|
||||
#include "WDC65816InstrInfo.h"
|
||||
#include "WDC65816SelectionDAGInfo.h"
|
||||
#include "llvm/IR/DataLayout.h"
|
||||
#include "llvm/Target/TargetFrameLowering.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class WDC65816TargetMachine : public LLVMTargetMachine {
|
||||
// SparcSubtarget Subtarget; JSR_TODO - Do I need this?
|
||||
const DataLayout DL; // Calculates type size & alignment
|
||||
WDC65816InstrInfo InstrInfo;
|
||||
WDC65816TargetLowering TLInfo;
|
||||
WDC65816SelectionDAGInfo TSInfo;
|
||||
WDC65816FrameLowering FrameLowering;
|
||||
public:
|
||||
WDC65816TargetMachine(const Target &T, StringRef TT,
|
||||
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
||||
Reloc::Model RM, CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL);
|
||||
|
||||
virtual const WDC65816InstrInfo *getInstrInfo() const { return &InstrInfo; }
|
||||
virtual const TargetFrameLowering *getFrameLowering() const {
|
||||
return &FrameLowering;
|
||||
}
|
||||
virtual const WDC65816RegisterInfo *getRegisterInfo() const {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
virtual const WDC65816TargetLowering* getTargetLowering() const {
|
||||
return &TLInfo;
|
||||
}
|
||||
virtual const WDC65816SelectionDAGInfo* getSelectionDAGInfo() const {
|
||||
return &TSInfo;
|
||||
}
|
||||
virtual const DataLayout *getDataLayout() const { return &DL; }
|
||||
|
||||
// Pass Pipeline Configuration
|
||||
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
||||
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue