Make a step towards getting memory reads working.
This commit is contained in:
Jeremy Rand
parent
f8d884f5f9
commit
3def47d32f
File diff suppressed because it is too large
Load Diff
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@ -22,7 +22,8 @@ namespace llvm {
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namespace WDCISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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RET_FLAG // Return with a flag operand.
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RET_FLAG, // Return with a flag operand.
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Wrapper
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#if 0
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CMPICC, // Compare two GPR operands, set icc+xcc.
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CMPFCC, // Compare two FP operands, set fcc.
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@ -71,97 +72,15 @@ namespace llvm {
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SDLoc dl, SelectionDAG &DAG) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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#if 0 // WDC_TODO - Do I need any of this?
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
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SDValue LowerFormalArguments_32(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerFormalArguments_64(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerReturn_32(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const;
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SDValue LowerReturn_64(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
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SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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SelectionDAG &DAG) const;
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SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
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SDValue Arg, SDLoc DL,
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SelectionDAG &DAG) const;
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SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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const char *LibFuncName,
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unsigned numArgs) const;
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SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
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unsigned &SPCC,
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SDLoc DL,
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SelectionDAG &DAG) const;
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bool ShouldShrinkFPConstant(EVT VT) const {
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// Do not shrink FP constpool if VT == MVT::f128.
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// (ldd, call _Q_fdtoq) is more expensive than two ldds.
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return VT != MVT::f128;
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}
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virtual void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>& Results,
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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#endif
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virtual void LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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};
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} // end namespace llvm
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@ -17,6 +17,14 @@
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include "WDC65816InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// WDC65816 specific DAG Nodes.
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//
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def SDTWDCWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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def WDCWrapper : SDNode<"WDCISD::Wrapper", SDTWDCWrapper>;
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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@ -1414,3 +1422,8 @@ def XCE : Group3<OpGrp3XCE,
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// GlobalAddress, ExternalSymbol
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def : Pat<(i16 (WDCWrapper tglobaladdr:$dst)), (LDAabsl tglobaladdr:$dst)>;
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def : Pat<(i16 (WDCWrapper texternalsym:$dst)), (LDAabsl texternalsym:$dst)>;
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def : Pat<(i16 (WDCWrapper tblockaddress:$dst)), (LDAabsl tblockaddress:$dst)>;
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