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https://github.com/jeremysrand/llvm-65816.git
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Add some more debug around which node is being visited.
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@ -174,6 +174,8 @@ SDNode *WDC65816DAGToDAGISel::Select(SDNode *N) {
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}
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}
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WDC_LOG("WDC_TODO - Unimplemented method called, opcode=" << N->getOpcode());
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WDC_LOG("WDC_TODO - Unimplemented method called, opcode=" << N->getOpcode());
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// Uncomment the following line to see the node info.
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// N->dumprFull(CurDAG);
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switch (N->getOpcode()) {
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switch (N->getOpcode()) {
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default: break;
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default: break;
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@ -1102,34 +1102,16 @@ WDC65816TargetLowering::WDC65816TargetLowering(TargetMachine &TM)
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#endif
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#endif
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}
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}
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#if 0 // WDC_TODO - Disable this stuff for now...
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const char *WDC65816TargetLowering::getTargetNodeName(unsigned Opcode) const {
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const char *WDC65816TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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switch (Opcode) {
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default: return 0;
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default: return 0;
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case SPISD::CMPICC: return "SPISD::CMPICC";
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case WDCISD::RET_FLAG: return "WDCSD::RET_FLAG";
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case SPISD::CMPFCC: return "SPISD::CMPFCC";
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case SPISD::BRICC: return "SPISD::BRICC";
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case SPISD::BRXCC: return "SPISD::BRXCC";
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case SPISD::BRFCC: return "SPISD::BRFCC";
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case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
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case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
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case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
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case SPISD::Hi: return "SPISD::Hi";
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case SPISD::Lo: return "SPISD::Lo";
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case SPISD::FTOI: return "SPISD::FTOI";
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case SPISD::ITOF: return "SPISD::ITOF";
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case SPISD::FTOX: return "SPISD::FTOX";
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case SPISD::XTOF: return "SPISD::XTOF";
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case SPISD::CALL: return "SPISD::CALL";
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case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
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case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
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case SPISD::FLUSHW: return "SPISD::FLUSHW";
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case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
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case SPISD::TLS_LD: return "SPISD::TLS_LD";
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case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
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}
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}
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}
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}
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#if 0 // WDC_TODO - Disable this stuff for now...
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EVT WDC65816TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
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EVT WDC65816TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
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if (!VT.isVector())
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if (!VT.isVector())
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return MVT::i32;
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return MVT::i32;
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@ -70,6 +70,8 @@ namespace llvm {
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const;
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SDLoc dl, SelectionDAG &DAG) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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#if 0 // WDC_TODO - Do I need any of this?
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#if 0 // WDC_TODO - Do I need any of this?
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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@ -86,7 +88,6 @@ namespace llvm {
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EmitInstrWithCustomInserter(MachineInstr *MI,
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *MBB) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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std::pair<unsigned, const TargetRegisterClass*>
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