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79 lines
2.1 KiB
Markdown
79 lines
2.1 KiB
Markdown
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[< back to index](../index.md)
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# 8086 support disclaimer
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Millfork does not support Intel 8086 directly.
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Instead, it generates Intel 8080 code and translates it automatically to 8086 machine code.
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For convenience, Z80 instructions using `IX` are also translated.
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This means that:
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* code is going to be large and slow;
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* there is no support for writing 8086 assembly;
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* Millfork currently translates majority of Intel 8080 assembly instructions to 8086 machine code,
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so you can write 8080/Z80 assembly instead.
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For example, code like
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asm {
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LD HL, x
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LD BC, i
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ADD HL, BC
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JP C, skip
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LD A, IX(5)
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LD (HL), A
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skip:
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}
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is compiled to
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MOV BX, x
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MOV CX, i
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ADD BX, CX
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JNC .next
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JMP skip
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.next:
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MOV AL, BYTE PTR [BP+5]
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MOV BYTE PTR [BX], AL
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skip:
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Generated assembly output uses Intel 8086 syntax.
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#### Major deficiencies of generated code
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* hardware multiplication is not used
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* many 16-bit operations are not used
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* many operations are restricted to the `AL` register
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* the overflow flag is not used
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* `DAS` is not used
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* conditional jumps are never optimized to short 2-byte jumps and always use 5 bytes
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* the `SI` register is reloaded before every use
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* the converter translates the `DAD` instruction (16-bit `ADD` on Z80) to `ADD`,
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which may change behaviour of assembly code,
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as 8080's `DAD` changes only the carry flag, and 8086's `ADD` changes many flags.
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Luckily, this is not an issue with Millfork code, as the optimizer does not assume anything about flags after that instruction.
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The proper sequence is `LAHF`/`ADD r1,r2`/`RCR SI,1`/`SAHF`/`RCL SI,1`, but it is obviously too slow.
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#### Register mapping
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The registers are translated as following:
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A → AL
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B → CH C → CL BC → CX
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D → DH E → DL DE → DX
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H → BH L → BL HL → BX
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SP → SP
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IX → BP
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The `SI` register is used as a temporary register for holding the address in `LDAX`/`STAX`
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(`LD (DE),A`/`LD(BC),A`/`LD A,(DE)`/`LD A,(BC)` on Z80).
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