From 010647682ae5c63e3a84464dd753f73e0fa7aa16 Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Wed, 23 Oct 2019 11:52:42 +0200
Subject: [PATCH] Fix the sieve benchmark

---
 CHANGELOG.md                                      |  4 ++++
 .../millfork/assembly/mos/opt/CpuStatus.scala     | 10 ++++++++++
 .../compiler/mos/PseudoregisterBuiltIns.scala     |  4 ++--
 src/main/scala/millfork/env/Constant.scala        |  2 +-
 src/test/scala/millfork/test/WordMathSuite.scala  | 15 +++++++++++++++
 5 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 055f5538..f778ce1d 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -22,6 +22,10 @@
 
 * Fixed a bug with variable overlapping (#11).
 
+* 6502: Fixed a bug with flow analysis during optimizations.
+
+* 6502: Fixed a bug with certain 16-bit additions.
+
 * 8080: Fixed and optimized 16-bit comparisons.
 
 * 8080: Optimized some library functions.
diff --git a/src/main/scala/millfork/assembly/mos/opt/CpuStatus.scala b/src/main/scala/millfork/assembly/mos/opt/CpuStatus.scala
index 3208c226..1eec0374 100644
--- a/src/main/scala/millfork/assembly/mos/opt/CpuStatus.scala
+++ b/src/main/scala/millfork/assembly/mos/opt/CpuStatus.scala
@@ -214,6 +214,8 @@ object CpuStatus {
         v = AnyStatus,
         z = AnyStatus,
         n = AnyStatus,
+        a0 = AnyStatus,
+        a7 = AnyStatus,
         d = SingleStatus(false),
         m = SingleStatus(true),
         w = SingleStatus(true),
@@ -231,6 +233,8 @@ object CpuStatus {
         v = AnyStatus,
         z = AnyStatus,
         n = AnyStatus,
+        a0 = AnyStatus,
+        a7 = AnyStatus,
         d = SingleStatus(false),
         m = SingleStatus(true),
         w = SingleStatus(true),
@@ -249,6 +253,8 @@ object CpuStatus {
         v = AnyStatus,
         z = AnyStatus,
         n = AnyStatus,
+        a0 = AnyStatus,
+        a7 = AnyStatus,
         d = AnyStatus,
         m = AnyStatus,
         w = AnyStatus,
@@ -266,6 +272,8 @@ object CpuStatus {
         v = AnyStatus,
         z = AnyStatus,
         n = AnyStatus,
+        a0 = AnyStatus,
+        a7 = AnyStatus,
         d = SingleStatus(false),
         m = AnyStatus,
         w = AnyStatus,
@@ -283,6 +291,8 @@ object CpuStatus {
         v = AnyStatus,
         z = AnyStatus,
         n = AnyStatus,
+        a0 = AnyStatus,
+        a7 = AnyStatus,
         d = SingleStatus(false),
         m = AnyStatus,
         w = AnyStatus,
diff --git a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
index e59f2a9c..f7f49aed 100644
--- a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
+++ b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
@@ -45,7 +45,7 @@ object PseudoregisterBuiltIns {
         case List(AssemblyLine0(LDA, Immediate, l), AssemblyLine0(LDX, Immediate, h)) =>
           if (subtract) constant -= h.asl(8).+(l).quickSimplify
           else constant += h.asl(8).+(l).quickSimplify
-        case List(l@AssemblyLine0(LDA, Absolute | ZeroPage | Immediate, _), h@AssemblyLine0(LDX, Absolute | ZeroPage | Immediate, _)) =>
+        case List(l@AssemblyLine0(LDA, Absolute | ZeroPage | Immediate | LongAbsolute, _), h@AssemblyLine0(LDX, Absolute | ZeroPage | Immediate | LongAbsolute, _)) =>
           if (subtract) niceReads.+=(List(AssemblyLine.implied(SEC), l.copy(opcode = SBC)) -> List(h.copy(opcode = SBC)))
           else niceReads += (List(AssemblyLine.implied(CLC), l.copy(opcode = ADC)) -> List(h.copy(opcode = ADC)))
           counter += 1
@@ -68,7 +68,7 @@ object PseudoregisterBuiltIns {
           if (constant.isQuiteNegative) {
             niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
           } else {
-            val negC = Constant.Zero.-(constant).quickSimplify.quickSimplify
+            val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
             niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
           }
         }
diff --git a/src/main/scala/millfork/env/Constant.scala b/src/main/scala/millfork/env/Constant.scala
index c0fec224..b8505cd2 100644
--- a/src/main/scala/millfork/env/Constant.scala
+++ b/src/main/scala/millfork/env/Constant.scala
@@ -40,7 +40,7 @@ sealed trait Constant {
     case _ => CompoundConstant(MathOperator.Shl, this, i)
   }
 
-  def asl(i: Int): Constant = CompoundConstant(MathOperator.Shl, this, NumericConstant(i, 1))
+  def asl(i: Int): Constant = CompoundConstant(MathOperator.Shl, this, NumericConstant(i, requiredSize + i/8))
 
   def requiredSize: Int
 
diff --git a/src/test/scala/millfork/test/WordMathSuite.scala b/src/test/scala/millfork/test/WordMathSuite.scala
index 639f8e02..e15caf4f 100644
--- a/src/test/scala/millfork/test/WordMathSuite.scala
+++ b/src/test/scala/millfork/test/WordMathSuite.scala
@@ -20,6 +20,21 @@ class WordMathSuite extends FunSuite with Matchers with AppendedClues {
       """.stripMargin)(_.readWord(0xc000) should equal(1280))
   }
 
+  test("Addition that was buggy") {
+    EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Z80, Cpu.Motorola6809)("""
+        | word output @$c000
+        | array X [$1000] align($100)
+        | void main () {
+        |  output = f(1)
+        | }
+        | noinline word f(byte I) {
+        |   word S
+        |   S = X + nonet(I << 1)
+        |   return S
+        | }
+      """.stripMargin)(_.readWord(0xc000) should equal(0x302))
+  }
+
   test("Cast word addition") {
     EmuCrossPlatformBenchmarkRun(Cpu.Sixteen, Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Intel8085, Cpu.Sharp, Cpu.Intel8086, Cpu.Motorola6809)("""
         | byte output @$c000