mirror of
https://github.com/KarolS/millfork.git
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Allow taking addresses of stack variables
This commit is contained in:
Karol Stasiak
parent
f22b62e57f
commit
0205520bf9
@ -30,6 +30,8 @@
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* Added `nullptr`.
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* You can now take a pointer to a stack variable.
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* Arrays can now have elements of types other than `byte` (still limited in size to 1 byte though) and be built out of struct literals.
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* Arrays can now be constant.
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@ -64,6 +66,8 @@
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* 8080 and LR35902: fixed large stack variables.
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* Other bug fixes.
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* Optimization improvements.
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## 0.3.2
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@ -42,7 +42,7 @@ but the main disadvantages are:
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* increased stack usage
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* cannot take their addresses
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* their addresses are not considered constants and it's slower to get them
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* cannot use them in inline assembly code blocks
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@ -1001,7 +1001,7 @@ object AlwaysGoodOptimizations {
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XContainsHardwareStackPointer & HasOpcodeIn(INC, DEC, ASL, LSR) & MatchAddrMode(0) & MatchParameter(1) |
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Linear & XContainsHardwareStackPointer & HasAddrMode(AbsoluteX) & Not(MatchParameter(1)) & Not(HasOpcodeIn(OpcodeClasses.AccessesWordInMemory)) |
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Linear & HasAddrMode(AbsoluteX) & Not(MatchParameter(1) & XContainsHardwareStackPointer) & Not(ChangesMemory) |
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Linear & Not(ChangesS) & DoesntChangeMemoryAt(0, 1) & Not(HasAddrMode(AbsoluteX))).* ~
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Linear & Not(ChangesS) & DoesntChangeMemoryAt(0, 1) & Not(HasAddrMode(AbsoluteX)) & Not(HasOpcodeIn(TXA, TXY, HuSAX, SXY, STX, STX_W, PHX, PHX_W, SAX, XAA, SAX, AHX, SHX, TAS))).* ~
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(Elidable & XContainsHardwareStackPointer & HasOpcodeIn(LDA, LDX, LDY, ADC, SBC, ORA, EOR, AND, CMP) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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val oldA = ctx.get[Int](2)
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val ADDR = ctx.get[Constant](1)
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@ -28,6 +28,13 @@ object CoarseFlowAnalyzer {
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val preservesE: Set[String] = Set("__divmod_u16u8u16u8")
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val preservesH: Set[String] = Set("__mul_u8u8u8")
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val preservesL: Set[String] = Set("__mul_u8u8u8")
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// does the code preserve the stack variables apart from direct writes, assuming Z80 and base pointer in IX?
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val preservesStackVariables = code.forall {
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case ZLine0(ZOpcode.ADD_16, TwoRegisters(ZRegister.HL, ZRegister.SP), _) => false
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case ZLine0(ZOpcode.ADD_16, TwoRegisters(ZRegister.IY, ZRegister.SP), _) => false
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case ZLine0(ZOpcode.ADD_16, TwoRegisters(ZRegister.IX, ZRegister.SP), _) => compilationOptions.flag(CompilationFlag.UseIxForStack)
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case _ => true
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}
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var changed = true
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while (changed) {
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@ -56,7 +63,7 @@ object CoarseFlowAnalyzer {
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case _ => true
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}
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if (mayBeCalled) {
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val result = initialStatus.copy(memIx = currentStatus.memIx)
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val result = if (preservesStackVariables) initialStatus.copy(memIx = currentStatus.memIx) else initialStatus
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currentStatus = result.copy(
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b = if (preservesB(n)) currentStatus.b else result.b,
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c = if (preservesC(n)) currentStatus.c else result.c,
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@ -144,19 +151,21 @@ object CoarseFlowAnalyzer {
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val newV = currentStatus.getRegister(r).map(i => i.+(1).&(0xff))
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currentStatus = currentStatus.
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copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus).
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setRegister(r, newV)
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setRegister(r, newV).
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cleanMemIxIfNeeded(preservesStackVariables, r)
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case ZLine0(DEC, OneRegister(r), _) =>
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val newV = currentStatus.getRegister(r).map(i => i.-(1).&(0xff))
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currentStatus = currentStatus.
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copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus).
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setRegister(r, newV)
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setRegister(r, newV).
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cleanMemIxIfNeeded(preservesStackVariables, r)
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case ZLine0(INC, OneRegisterOffset(r, o), _) =>
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val newV = currentStatus.getRegister(r, o).map(i => i.+(1).&(0xff))
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val newV = currentStatus.cleanMemIxIfNeeded(preservesStackVariables, r).getRegister(r, o).map(i => i.+(1).&(0xff))
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currentStatus = currentStatus.
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copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus).
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setRegister(r, newV, o)
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case ZLine0(DEC, OneRegisterOffset(r, o), _) =>
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val newV = currentStatus.getRegister(r, o).map(i => i.-(1).&(0xff))
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val newV = currentStatus.cleanMemIxIfNeeded(preservesStackVariables, r).getRegister(r, o).map(i => i.-(1).&(0xff))
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currentStatus = currentStatus.
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copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus).
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setRegister(r, newV, o)
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@ -174,21 +183,27 @@ object CoarseFlowAnalyzer {
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case ZLine0(LD_AHLI, _, _) =>
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val newHL = currentStatus.getRegister(ZRegister.HL).map(i => i.+(1).&(0xffff))
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currentStatus = currentStatus.copy(a = AnyStatus).setRegister(ZRegister.HL, newHL)
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currentStatus = currentStatus.copy(a = AnyStatus).setRegister(ZRegister.HL, newHL).
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cleanMemIxIfNeeded(preservesStackVariables, ZRegister.MEM_HL)
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case ZLine0(LD_HLIA, _, _) =>
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val newHL = currentStatus.getRegister(ZRegister.HL).map(i => i.+(1).&(0xffff))
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currentStatus = currentStatus.setRegister(ZRegister.HL, newHL)
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currentStatus = currentStatus.setRegister(ZRegister.HL, newHL).
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cleanMemIxIfNeeded(preservesStackVariables, ZRegister.MEM_HL)
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case ZLine0(LD_AHLD, _, _) =>
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val newHL = currentStatus.getRegister(ZRegister.HL).map(i => i.-(1).&(0xffff))
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currentStatus = currentStatus.copy(a = AnyStatus).setRegister(ZRegister.HL, newHL)
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currentStatus = currentStatus.copy(a = AnyStatus).setRegister(ZRegister.HL, newHL).
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cleanMemIxIfNeeded(preservesStackVariables, ZRegister.MEM_HL)
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case ZLine0(LD_HLDA, _, _) =>
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val newHL = currentStatus.getRegister(ZRegister.HL).map(i => i.-(1).&(0xffff))
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currentStatus = currentStatus.setRegister(ZRegister.HL, newHL)
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currentStatus = currentStatus.setRegister(ZRegister.HL, newHL).
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cleanMemIxIfNeeded(preservesStackVariables, ZRegister.MEM_HL)
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case ZLine0(op, OneRegister(r), _) if ZOpcodeClasses.SET(op) =>
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currentStatus = currentStatus.setRegister(r, currentStatus.getRegister(r).map(i => i | 1.<<(ZOpcodeClasses.SET_seq.indexOf(op))))
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currentStatus = currentStatus.setRegister(r, currentStatus.getRegister(r).map(i => i | 1.<<(ZOpcodeClasses.SET_seq.indexOf(op)))).
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cleanMemIxIfNeeded(preservesStackVariables, r)
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case ZLine0(op, OneRegister(r), _) if ZOpcodeClasses.RES(op) =>
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currentStatus = currentStatus.setRegister(r, currentStatus.getRegister(r).map(i => i & ~1.<<(ZOpcodeClasses.RES_seq.indexOf(op))))
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currentStatus = currentStatus.setRegister(r, currentStatus.getRegister(r).map(i => i & ~1.<<(ZOpcodeClasses.RES_seq.indexOf(op)))).
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cleanMemIxIfNeeded(preservesStackVariables, r)
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case l@ZLine0(ADD, OneRegisterOffset(s, o), _) =>
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val (newA, newC) = currentStatus.a.adc(currentStatus.getRegister(s, o), Status.SingleFalse)
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@ -221,11 +236,12 @@ object CoarseFlowAnalyzer {
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case ZLine0(LD, TwoRegisters(ZRegister.A, ZRegister.I | ZRegister.R), _) =>
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currentStatus = currentStatus.copy(a = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus, nf = AnyStatus)
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case ZLine0(LD, TwoRegisters(t, ZRegister.IMM_8), NumericConstant(value, _)) =>
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currentStatus = currentStatus.setRegister(t, SingleStatus(value.toInt))
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currentStatus = currentStatus.setRegister(t, SingleStatus(value.toInt)).
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cleanMemIxIfNeeded(preservesStackVariables, t)
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case ZLine0(LD, TwoRegistersOffset(t, ZRegister.IMM_8, o), NumericConstant(value, _)) =>
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currentStatus = currentStatus.setRegister(t, SingleStatus(value.toInt), o)
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currentStatus = currentStatus.cleanMemIxIfNeeded(preservesStackVariables, t).setRegister(t, SingleStatus(value.toInt), o)
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case ZLine0(LD | LD_16, TwoRegisters(t, s), _) =>
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currentStatus = currentStatus.setRegister(t, currentStatus.getRegister(s))
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currentStatus = currentStatus.setRegister(t, currentStatus.getRegister(s)).cleanMemIxIfNeeded(preservesStackVariables, t)
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case ZLine0(LD | LD_16, TwoRegistersOffset(t, s, o), _) =>
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currentStatus = currentStatus.setRegister(t, currentStatus.getRegister(s, o), o)
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case ZLine0(EX_DE_HL, _, _) =>
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@ -237,9 +253,11 @@ object CoarseFlowAnalyzer {
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case ZLine0(SLA, OneRegister(r), _) =>
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currentStatus = currentStatus.copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
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.setRegister(r, currentStatus.getRegister(r).map(_.<<(1).&(0xff)))
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.cleanMemIxIfNeeded(preservesStackVariables, r)
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case ZLine0(SRL, OneRegister(r), _) =>
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currentStatus = currentStatus.copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
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.setRegister(r, currentStatus.getRegister(r).map(_.>>(1).&(0x7f)))
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.cleanMemIxIfNeeded(preservesStackVariables, r)
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case ZLine0(RLA | RRA | RLCA | RRCA, _, _) =>
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@ -144,6 +144,12 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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case UnknownStatus => this.copy(l = UnknownStatus, h = UnknownStatus, hl = UnknownStatus)
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}
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def cleanMemIxIfNeeded(preservesStackVariables: Boolean, r: ZRegister.Value): CpuStatus = if (preservesStackVariables) this else {
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r match {
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case ZRegister.MEM_HL | ZRegister.MEM_BC | ZRegister.MEM_DE => copy(memIx = Map())
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case _ => this
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}
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}
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override def toString: String = {
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val memRepr = if (memIx.isEmpty) "" else (0 to memIx.keys.max).map(i => memIx.getOrElse(i, UnknownStatus)).mkString("")
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@ -41,7 +41,7 @@ object BuiltIns {
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val parts: (List[AssemblyLine], List[AssemblyLine]) = env.eval(source).fold {
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val b = env.get[Type]("byte")
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source match {
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case VariableExpression(name) =>
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case VariableExpression(name) if env.maybeGet[Variable](name).isDefined =>
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val v = env.get[Variable](name)
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if (v.typ.size > 1) {
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ctx.log.error(s"Variable `$name` is too big for a built-in operation", source.position)
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@ -447,6 +447,67 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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compileToZReg(ctx, pointerExpression) -> ctx.env.get[ThingInMemory]("__reg.loword")
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}
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def compileStackOffset(ctx: CompilationContext, target: Variable, offset: Int, subbyte: Option[Int]): List[AssemblyLine] = {
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val hi = if (ctx.options.flag(CompilationFlag.SoftwareStack)) {
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MemoryAddressConstant(ctx.env.get[ThingInMemory]("__stack")).hiByte
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} else {
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Constant.One
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}
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val tsx = if (ctx.options.flag(CompilationFlag.SoftwareStack)) {
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AssemblyLine.absolute(LDX, MemoryAddressConstant(ctx.env.get[ThingInMemory]("__sp")))
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} else {
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AssemblyLine.implied(TSX)
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}
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val actualOffset = if (ctx.options.flag(CompilationFlag.SoftwareStack)) {
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offset & 0xff
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} else {
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(offset + ctx.extraStackOffset) & 0xff
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}
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val b = ctx.env.get[Type]("byte")
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subbyte match {
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case Some(1) => compile(ctx, GeneratedConstantExpression(hi, b), Some(b -> target), BranchSpec.None)
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case Some(0) => target match {
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case RegisterVariable(MosRegister.A, _) => actualOffset match {
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case 0 => List(tsx, AssemblyLine.implied(TXA))
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case 1 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(TXA))
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case 2 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(INX), AssemblyLine.implied(TXA))
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case _ => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, actualOffset))
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}
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case RegisterVariable(MosRegister.X, _) => actualOffset match {
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case 0 => List(tsx)
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case 1 => List(tsx, AssemblyLine.implied(INX))
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case 2 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(INX))
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case 3 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(INX), AssemblyLine.implied(INX))
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case _ => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, actualOffset), AssemblyLine.implied(TAX))
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}
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case RegisterVariable(MosRegister.Y, _) => actualOffset match {
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case 0 => List(tsx)
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case 1 => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(TAY), AssemblyLine.implied(INY))
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case _ => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, actualOffset), AssemblyLine.implied(TAY))
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}
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case _ =>
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val loadA = actualOffset match {
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case 0 => List(tsx, AssemblyLine.implied(TXA))
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case 1 => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(INX))
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case 2 => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(INX), AssemblyLine.implied(INX))
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case _ => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, actualOffset))
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}
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loadA ++ expressionStorageFromA(ctx, Some(b -> target), None)
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}
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case None =>
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val loadA = actualOffset match {
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case 0 => List(tsx, AssemblyLine.implied(TXA))
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case 1 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(TXA))
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case 2 => List(tsx, AssemblyLine.implied(INX), AssemblyLine.implied(INX), AssemblyLine.implied(TXA))
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case _ => List(tsx, AssemblyLine.implied(TXA), AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, actualOffset))
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}
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loadA ++ List(AssemblyLine.immediate(LDX, hi)) ++ expressionStorageFromAX(ctx, Some(ctx.env.get[Type]("pointer") -> target), None)
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case _ => throw new IllegalArgumentException
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}
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}
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def compile(ctx: CompilationContext, expr: Expression, exprTypeAndVariable: Option[(Type, Variable)], branches: BranchSpec): List[AssemblyLine] = {
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val env = ctx.env
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env.eval(expr) match {
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@ -476,6 +537,7 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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assertCompatible(exprType, target.typ)
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env.eval(expr).map(c => compileConstant(ctx, c, target)).getOrElse {
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env.get[TypedThing](name) match {
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case source: StackOffsetThing => compileStackOffset(ctx, target, source.offset, source.subbyte)
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case source: VariableInMemory =>
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target match {
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case RegisterVariable(MosRegister.A, _) => AssemblyLine.variable(ctx, LDA, source)
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@ -253,7 +253,14 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
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case LiteralExpression(value, _) => ???
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case GeneratedConstantExpression(_, _) => ???
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case VariableExpression(name) =>
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env.get[Variable](name) match {
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env.get[VariableLikeThing](name) match {
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case s: StackOffsetThing =>
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s.subbyte match {
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case None => targetifyHL(ctx, target, calculateStackAddressToHL(ctx, s.offset))
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case Some(0) => targetifyA(ctx, target, calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.L), isSigned = false)
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case Some(1) => targetifyA(ctx, target, calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.H), isSigned = false)
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case _ => throw new IllegalArgumentException
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}
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case v: VariableInMemory =>
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import ZRegister._
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v.typ.size match {
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@ -1139,7 +1146,8 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
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def calculateStackAddressToHL(ctx: CompilationContext, baseOffset: Int): List[ZLine] = {
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if (ctx.options.flag(CompilationFlag.UseIxForStack) || ctx.options.flag(CompilationFlag.UseIyForStack)) {
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???
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// TODO: is this correct?
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List(ZLine.ldImm16(ZRegister.HL, baseOffset + ctx.extraStackOffset), ZLine.registers(ZOpcode.ADD_16, ZRegister.HL, ZRegister.SP))
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} else if (ctx.options.flag(CompilationFlag.EmitSharpOpcodes)) {
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List(ZLine.imm8(ZOpcode.LD_HLSP, baseOffset + ctx.extraStackOffset))
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} else {
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@ -1592,7 +1600,22 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
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case None =>
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rhs match {
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case VariableExpression(vname) =>
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env.get[Variable](vname) match {
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env.get[VariableLikeThing](vname) match {
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case s: StackOffsetThing =>
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s.subbyte match {
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case None =>
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val list = List(
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calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.L),
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calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.H)) ++ List.fill(size)(List(ZLine.ldImm8(ZRegister.A, 0)))
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list.take(size)
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case Some(0) =>
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val list = (calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.L)) :: List.fill(size)(List(ZLine.ldImm8(ZRegister.A, 0)))
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list.take(size)
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case Some(1) =>
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val list = (calculateStackAddressToHL(ctx, s.offset) :+ ZLine.ld8(ZRegister.A, ZRegister.H)) :: List.fill(size)(List(ZLine.ldImm8(ZRegister.A, 0)))
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list.take(size)
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case _ => throw new IllegalArgumentException
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}
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case v: VariableInMemory =>
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List.tabulate(size) { i =>
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if (i < v.typ.size) {
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@ -1471,6 +1471,12 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
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if (stmt.stack) {
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val v = StackVariable(prefix + name, typ, this.baseStackOffset)
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addVariable(options, name, v, stmt.position)
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addThing(StackOffsetThing(v.name + ".addr", this.baseStackOffset, get[Type]("pointer"), None), stmt.position)
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addThing(StackOffsetThing(v.name + ".addr.lo", this.baseStackOffset, b, Some(0)), stmt.position)
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addThing(StackOffsetThing(v.name + ".addr.hi", this.baseStackOffset, b, Some(1)), stmt.position)
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addThing(StackOffsetThing(v.name + ".pointer", this.baseStackOffset, PointerType("pointer."+v.typ.name, v.typ.name, Some(v.typ)), None), stmt.position)
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addThing(StackOffsetThing(v.name + ".pointer.lo", this.baseStackOffset, b, Some(0)), stmt.position)
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addThing(StackOffsetThing(v.name + ".pointer.hi", this.baseStackOffset, b, Some(1)), stmt.position)
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baseStackOffset += typ.size
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} else {
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val (v, addr) = stmt.address.fold[(VariableInMemory, Constant)]({
|
||||
@ -1736,7 +1742,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
||||
if (options.flag(CompilationFlag.SoftwareStack)) {
|
||||
if (!things.contains("__sp")) {
|
||||
things("__sp") = UninitializedMemoryVariable("__sp", b, VariableAllocationMethod.Auto, None, NoAlignment, isVolatile = false)
|
||||
things("__stack") = UninitializedArray("__stack", 256, None, b, b, readOnly = false, WithinPageAlignment)
|
||||
things("__stack") = UninitializedArray("__stack", 256, None, b, b, readOnly = false, DivisibleAlignment(256))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
4
src/main/scala/millfork/env/Thing.scala
vendored
4
src/main/scala/millfork/env/Thing.scala
vendored
@ -383,6 +383,10 @@ case class ConstantThing(name: String, value: Constant, typ: Type) extends Typed
|
||||
def map(f: Constant => Constant) = ConstantThing("", f(value), typ)
|
||||
}
|
||||
|
||||
case class StackOffsetThing(name: String, offset: Int, typ: Type, subbyte: Option[Int]) extends TypedThing with VariableLikeThing {
|
||||
|
||||
}
|
||||
|
||||
trait ParamSignature {
|
||||
def types: List[Type]
|
||||
|
||||
|
||||
@ -290,4 +290,105 @@ class StackVarSuite extends FunSuite with Matchers {
|
||||
m.readLong(0xc000) should equal(400)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
test("Pointers to stack variables 1") {
|
||||
val code =
|
||||
"""
|
||||
| noinline void inc(pointer.byte p) {
|
||||
| p[0] += 1
|
||||
| test1 = word(p)
|
||||
| }
|
||||
| byte output @$c000
|
||||
| word test1 @$c002
|
||||
| word stkptr @$c004
|
||||
| void main () {
|
||||
| stack byte a
|
||||
| a = 0
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| inc(a.pointer) // ↑
|
||||
| output = a
|
||||
| #if ARCH_6502
|
||||
| asm {
|
||||
| tsx
|
||||
| stx stkptr
|
||||
| ldx #0
|
||||
| stx stkptr+1
|
||||
| }
|
||||
| #endif
|
||||
| #if ARCH_I80 && CPUFEATURE_8080
|
||||
| #pragma zilog_syntax
|
||||
| asm {
|
||||
| ld hl,0
|
||||
| add hl,sp
|
||||
| ld (stkptr),hl
|
||||
| }
|
||||
| #endif
|
||||
| #if CPUFEATURE_GAMEBOY
|
||||
| #pragma zilog_syntax
|
||||
| asm {
|
||||
| ld hl,0
|
||||
| add hl,sp
|
||||
| ld a,l
|
||||
| ld (stkptr),a
|
||||
| ld a,h
|
||||
| ld (stkptr+1),a
|
||||
| }
|
||||
| #endif
|
||||
| }
|
||||
""".stripMargin
|
||||
|
||||
EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Cmos, Cpu.Z80, Cpu.Intel8080, Cpu.Sharp)(code) { m =>
|
||||
println("$" + m.readWord(0xc002).toHexString)
|
||||
// (0x1f0 until 0x200).foreach { a =>
|
||||
// printf(f"$$$a%04x = $$${m.readByte(a)}%02x%n");
|
||||
// }
|
||||
// (0xc000 until 0xc010).foreach { a =>
|
||||
// printf(f"$$$a%04x = $$${m.readByte(a)}%02x%n");
|
||||
// }
|
||||
println("$" + m.readWord(0xc004).toHexString)
|
||||
m.readByte(0xc000) should equal(code.count(_ == '↑'))
|
||||
}
|
||||
EmuSoftwareStackBenchmarkRun(code) { m =>
|
||||
println("$" + m.readWord(0xc002).toHexString)
|
||||
println("$" + m.readWord(0xc004).toHexString)
|
||||
m.readByte(0xc000) should equal(code.count(_ == '↑'))
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
test("Pointers to stack variables 2") {
|
||||
val code =
|
||||
"""
|
||||
| import zp_reg
|
||||
| void main () {
|
||||
| stack byte a
|
||||
| a = 0
|
||||
| byte b
|
||||
| word w
|
||||
| b += a.addr.lo
|
||||
| w += a.addr
|
||||
| w <<= a.addr.hi
|
||||
| b *= a.addr.lo
|
||||
| b <<= a.addr.lo
|
||||
| w = nonet(b << a.addr.lo)
|
||||
| w &= a.addr
|
||||
| w = w | a.addr
|
||||
|
|
||||
| }
|
||||
""".stripMargin
|
||||
|
||||
EmuUnoptimizedCrossPlatformRun(Cpu.Mos, Cpu.Z80)(code) { m =>
|
||||
}
|
||||
EmuSoftwareStackBenchmarkRun(code) { m =>
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user