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Z80: Better inlining of variables into register pairs
This commit is contained in:
Karol Stasiak
parent
019547aae8
commit
0cb91c0f68
@ -1,7 +1,7 @@
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package millfork.assembly.z80.opt
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import millfork.assembly.AssemblyOptimization
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import millfork.assembly.z80.{opt, _}
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import millfork.assembly.z80._
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import millfork.assembly.z80.ZOpcode._
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import millfork.env.{CompoundConstant, Constant, MathOperator, NumericConstant}
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import millfork.node.ZRegister
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@ -786,6 +786,25 @@ object AlwaysGoodI80Optimizations {
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(Elidable & Is8BitLoadTo(ZRegister.C) & MatchImmediate(0)) ~~> { (code, ctx) =>
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List(ZLine.ldImm16(ZRegister.BC, (ctx.get[Constant](0) + ctx.get[Constant](1).asl(8)).quickSimplify))
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},
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// TODO: this is a bit controversial
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// 41 cycles 6 bytes → 24 cycles 8 bytes
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MultipleAssemblyRules(Seq(BC, DE).map{ reg =>
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(reg)) ~
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(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(reg, IMM_16)) & MatchParameter(0)) ~
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(Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(HL, reg))) ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(reg) & DoesntMatterWhatItDoesWithFlagsExceptCarry & DoesntMatterWhatItDoesWith(A)) ~~> { (code, ctx) =>
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val offset = ctx.get[Constant](0)
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List(
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ZLine.ld8(A, L),
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ZLine.imm8(ADD, offset.loByte),
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ZLine.ld8(L, A),
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ZLine.ld8(A, H),
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ZLine.imm8(ADC, offset.hiByte),
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ZLine.ld8(H, A)
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)
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}
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})
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)
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val UnusedCodeRemoval = new RuleBasedAssemblyOptimization("Unreachable code removal",
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@ -124,7 +124,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register pair HL")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars(v, "", "", oldCode.map(_._2))
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val newCode = inlineVars(v, "", "", oldCode)
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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@ -138,7 +138,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register pair BC")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars("", v, "", oldCode.map(_._2))
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val newCode = inlineVars("", v, "", oldCode)
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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@ -153,7 +153,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register pair DE")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars("", "", v, oldCode.map(_._2))
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val newCode = inlineVars("", "", v, oldCode)
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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@ -192,15 +192,16 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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None
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}
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code match {
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case (_, ZLine(LD_16, TwoRegisters(BC, IMM_16), _, true))::
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(i, ZLine(ADD_16, TwoRegisters(HL, BC), _, true)) :: xs if target == BC =>
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if (i.importanceAfter.getRegister(BC) == Important || i.importanceAfter.getRegister(DE) == Important) fail(22)
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if (i.importanceAfter.getRegister(BC) == Important) fail(22)
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else if(i.importanceAfter.getRegister(DE) == Important) canBeInlined(vname, synced, target, xs).map(add(CyclesAndBytes(-21, -2)))
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else canBeInlined(vname, synced = true, target, xs)
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case (_, ZLine(LD_16, TwoRegisters(DE, IMM_16), _, true))::
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(i, ZLine(ADD_16, TwoRegisters(HL, DE), _, true)) :: xs if target == DE =>
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if (i.importanceAfter.getRegister(BC) == Important || i.importanceAfter.getRegister(DE) == Important) fail(23)
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if (i.importanceAfter.getRegister(DE) == Important) fail(23)
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else if (i.importanceAfter.getRegister(BC) == Important) canBeInlined(vname, synced, target, xs).map(add(CyclesAndBytes(-21, -2)))
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else canBeInlined(vname, synced = true, target, xs)
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th1), true)) ::
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@ -292,28 +293,36 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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}
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}
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def inlineVars(hl: String, bc: String, de: String, code: List[ZLine]): List[ZLine] = {
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// if (code.nonEmpty) println(code.head)
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def inlineVars(hl: String, bc: String, de: String, code: List[(FlowInfo, ZLine)]): List[ZLine] = {
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// if (code.nonEmpty) println(code.head)
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code match {
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case (load@ZLine(LD_16, TwoRegisters(BC, IMM_16), _, _)) ::
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ZLine(ADD_16, TwoRegisters(HL, BC), _, _) ::
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case (_, load@ZLine(LD_16, TwoRegisters(BC, IMM_16), _, _)) ::
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(f, add@ZLine(ADD_16, TwoRegisters(HL, BC), _, _)) ::
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xs if bc != "" =>
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load.copy(registers = TwoRegisters(DE, IMM_16)) ::
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ZLine.registers(ADD_16, HL, DE) ::
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inlineVars(hl, bc, de, xs)
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if (f.importanceAfter.getRegister(DE) == Important) {
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ZLine.register(PUSH, BC) :: load :: add :: ZLine.register(POP, BC) :: inlineVars(hl, bc, de, xs)
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} else {
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load.copy(registers = TwoRegisters(DE, IMM_16)) ::
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ZLine.registers(ADD_16, HL, DE) ::
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inlineVars(hl, bc, de, xs)
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}
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case (load@ZLine(LD_16, TwoRegisters(DE, IMM_16), _, _)) ::
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ZLine(ADD_16, TwoRegisters(HL, DE), _, _) ::
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case (_, load@ZLine(LD_16, TwoRegisters(DE, IMM_16), _, _)) ::
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(f, add@ZLine(ADD_16, TwoRegisters(HL, DE), _, _)) ::
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xs if de != "" =>
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load.copy(registers = TwoRegisters(BC, IMM_16)) ::
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ZLine.registers(ADD_16, HL, BC) ::
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inlineVars(hl, bc, de, xs)
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if (f.importanceAfter.getRegister(BC) == Important) {
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ZLine.register(PUSH, DE) :: load :: add :: ZLine.register(POP, DE) :: inlineVars(hl, bc, de, xs)
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} else {
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load.copy(registers = TwoRegisters(BC, IMM_16)) ::
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ZLine.registers(ADD_16, HL, BC) ::
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inlineVars(hl, bc, de, xs)
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}
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case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), a1@MemoryAddressConstant(th1), _) ::
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ZLine(ADD_16, TwoRegisters(HL, reg@(DE | BC)), _, _) ::
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ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), a2@MemoryAddressConstant(th2), _) ::
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xs if hl != "" && th1.name != hl && th2.name != hl =>
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), a1@MemoryAddressConstant(th1), _)) ::
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(_, ZLine(ADD_16, TwoRegisters(HL, reg@(DE | BC)), _, _)) ::
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(_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), a2@MemoryAddressConstant(th2), _)) ::
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xs if hl != "" && th1.name != hl && th2.name != hl=>
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// bytes before: 3 + 1 + 3 = 7
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// cycles before: 16 + 11 + 16 = 43
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// bytes after: 3 + 1 + 3 + 3 + 1 + 3 = 14
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@ -330,99 +339,105 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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ZLine.ldAbs8(a2 + 1, A) ::
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) ::
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(loadConst@ZLine(LD_16, TwoRegisters(BC, constSource), _, _)) ::
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(add@ZLine(ADD_16, TwoRegisters(HL, BC), _, _)) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _)) ::
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(_, loadConst@ZLine(LD_16, TwoRegisters(BC, constSource), _, _)) ::
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(_, add@ZLine(ADD_16, TwoRegisters(HL, BC), _, _)) :: xs if th.name == bc =>
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ZLine.ld8(B, H) :: ZLine.ld8(C, L) ::
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loadConst.copy(registers = TwoRegisters(HL, constSource)) ::
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add.copy(registers = TwoRegisters(HL, BC)) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) ::
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(loadConst@ZLine(LD_16, TwoRegisters(DE, constSource), _, _)) ::
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(add@ZLine(ADD_16, TwoRegisters(HL, DE), _, _)) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _)) ::
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(_, loadConst@ZLine(LD_16, TwoRegisters(DE, constSource), _, _)) ::
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(_, add@ZLine(ADD_16, TwoRegisters(HL, DE), _, _)) :: xs if th.name == de =>
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ZLine.ld8(D, H) :: ZLine.ld8(E, L) ::
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loadConst.copy(registers = TwoRegisters(HL, constSource)) ::
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add.copy(registers = TwoRegisters(HL, DE)) :: inlineVars(hl, bc, de, xs)
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// TODO: above with regs swapped
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case (loadConst@ZLine(LD_16, TwoRegisters(t, constSource), _, _)) ::
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ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) ::
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(add@ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) :: xs if th.name == bc && t == t2 && t != HL =>
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case (_, loadConst@ZLine(LD_16, TwoRegisters(t, constSource), _, _)) ::
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(_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _)) ::
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(_, add@ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) :: xs if th.name == bc && t == t2 && t != HL =>
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loadConst.copy(registers = TwoRegisters(HL, constSource)) ::
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add.copy(registers = TwoRegisters(HL, BC)) :: inlineVars(hl, bc, de, xs)
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case (loadConst@ZLine(LD_16, TwoRegisters(t, constSource),_,_)) ::
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ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) ::
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(add@ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) :: xs if th.name == de && t == t2 && t != HL =>
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case (_, loadConst@ZLine(LD_16, TwoRegisters(t, constSource),_,_)) ::
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(_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _)) ::
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(_, add@ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) :: xs if th.name == de && t == t2 && t != HL =>
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loadConst.copy(registers = TwoRegisters(HL, constSource)) ::
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add.copy(registers = TwoRegisters(HL, DE)) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(H, B) :: ZLine.ld8(L, C) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(B, H) :: ZLine.ld8(C, L) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(H, D) :: ZLine.ld8(L, E) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(D, H) :: ZLine.ld8(E, L) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(D, B) :: ZLine.ld8(E, C) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(B, D) :: ZLine.ld8(C, E) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(DE, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(D, H) :: ZLine.ld8(E, L) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(H, D) :: ZLine.ld8(L, E) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(B, H) :: ZLine.ld8(C, L) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(H, B) :: ZLine.ld8(L, C) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(BC, MEM_ABS_16), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(B, D) :: ZLine.ld8(C, E) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(D, B) :: ZLine.ld8(E, C) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(A, L) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) :: xs if th.name == hl =>
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case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) ) :: xs if th.name == hl =>
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ZLine.ld8(L, A) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(A, C) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) :: xs if th.name == bc =>
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case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) ) :: xs if th.name == bc =>
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ZLine.ld8(C, A) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(A, E) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) :: xs if th.name == de =>
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case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _) ) :: xs if th.name == de =>
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ZLine.ld8(E, A) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == hl =>
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case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == hl =>
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ZLine.ld8(A, H) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == hl =>
|
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case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == hl =>
|
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ZLine.ld8(H, A) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == bc =>
|
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case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == bc =>
|
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ZLine.ld8(A, B) :: inlineVars(hl, bc, de, xs)
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case ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == bc =>
|
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case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == bc =>
|
||||
ZLine.ld8(B, A) :: inlineVars(hl, bc, de, xs)
|
||||
case ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == de =>
|
||||
case (_, ZLine(LD, TwoRegisters(A, MEM_ABS_8), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == de =>
|
||||
ZLine.ld8(A, D) :: inlineVars(hl, bc, de, xs)
|
||||
case ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) :: xs if th.name == de =>
|
||||
case (_, ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1, _)), _) ) :: xs if th.name == de =>
|
||||
ZLine.ld8(D, A) :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case (x@ZLine(CALL, _, _, _)) :: xs =>
|
||||
case (_, l1@ZLine(LD_16, TwoRegisters(BC, IMM_16), _, _)) :: (_, l2@ZLine(ADD_16, TwoRegisters(HL, BC), _, _)) :: xs if bc != "" =>
|
||||
ZLine.register(PUSH, BC) :: l1 :: l2 :: ZLine.register(POP, BC) :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case (_, l1@ZLine(LD_16, TwoRegisters(DE, IMM_16), _, _)) :: (_, l2@ZLine(ADD_16, TwoRegisters(HL, DE), _, _)) :: xs if de != "" =>
|
||||
ZLine.register(PUSH, DE) :: l1 :: l2 :: ZLine.register(POP, DE) :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case (_, x@ZLine(CALL, _, _, _)) :: xs =>
|
||||
if (bc != "") {
|
||||
ZLine.register(PUSH, BC) :: x :: ZLine.register(POP, BC) :: inlineVars(hl, bc, de, xs)
|
||||
} else if (de != "") {
|
||||
@ -432,18 +447,18 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
|
||||
}
|
||||
|
||||
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) :: xs if x.changesRegister(HL) && th.name == hl =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) :: xs if x.changesRegister(BC) && th.name == bc =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) :: xs if x.changesRegister(DE) && th.name == de =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _)) :: xs if x._2.changesRegister(HL) && th.name == hl =>
|
||||
x._2 :: inlineVars(hl, bc, de, xs)
|
||||
case x :: (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _)) :: xs if x._2.changesRegister(BC) && th.name == bc =>
|
||||
x._2 :: inlineVars(hl, bc, de, xs)
|
||||
case x :: (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _)) :: xs if x._2.changesRegister(DE) && th.name == de =>
|
||||
x._2 :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case x :: _ if bc != "" && x.changesRegister(BC) => throw new IllegalStateException()
|
||||
case x :: _ if de != "" && x.changesRegister(DE) => throw new IllegalStateException()
|
||||
case x :: _ if hl != "" && x.changesRegister(HL) => throw new IllegalStateException()
|
||||
case x :: _ if bc != "" && x._2.changesRegister(BC) => throw new IllegalStateException()
|
||||
case x :: _ if de != "" && x._2.changesRegister(DE) => throw new IllegalStateException()
|
||||
case x :: _ if hl != "" && x._2.changesRegister(HL) => throw new IllegalStateException()
|
||||
|
||||
case x :: xs => x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: xs => x._2 :: inlineVars(hl, bc, de, xs)
|
||||
case Nil => Nil
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user