6502/millfork
1
0
Fork 0
mirror of https://github.com/KarolS/millfork.git synced 2024-06-30 21:29:36 +00:00
Code Issues Projects Releases Wiki Activity

Fix for a bug in the variable-to-register optimization

Browse Source
This commit is contained in:
Karol Stasiak 2018-02-26 16:44:28 +01:00
parent 3c3ac9d70e
commit 0f354d2f14
1 changed files with 5 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/main/scala/millfork/assembly/opt/VariableToRegisterOptimization.scala
View File

@ -53,6 +53,9 @@ object VariableToRegisterOptimization extends AssemblyOptimization {
AHX, SHY, SHX, LAS, TAS,
TRB, TSB)
private val LdxAddrModes = Set(ZeroPage, Absolute, Immediate, AbsoluteY, ZeroPageY)
private val LdyAddrModes = Set(ZeroPage, Absolute, Immediate, AbsoluteX, ZeroPageX)
override def name = "Allocating variables to index registers"
@ -543,12 +546,12 @@ object VariableToRegisterOptimization extends AssemblyOptimization {
AssemblyLine.implied(TAY) :: inlineVars(xCandidate, yCandidate, aCandidate, xs)
case (AssemblyLine(LDA, am, param, true), _) :: (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), true), _) :: xs
if th.name == vx && doesntUseX(am) =>
if th.name == vx && LdxAddrModes(am) =>
// these TXA's may get optimized away by a different optimization
AssemblyLine(LDX, am, param) :: AssemblyLine.implied(TXA) :: inlineVars(xCandidate, yCandidate, aCandidate, xs)
case (AssemblyLine(LDA, am, param, true), _) :: (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), true), _) :: xs
if th.name == vy && doesntUseY(am) =>
if th.name == vy && LdyAddrModes(am) =>
// these TYA's may get optimized away by a different optimization
AssemblyLine(LDY, am, param) :: AssemblyLine.implied(TYA) :: inlineVars(xCandidate, yCandidate, aCandidate, xs)
@ -624,16 +627,6 @@ object VariableToRegisterOptimization extends AssemblyOptimization {
}
}
def doesntUseY(am: AddrMode.Value): Boolean = am match {
case AbsoluteY | ZeroPageY | IndexedY => false
case _ => true
}
def doesntUseX(am: AddrMode.Value): Boolean = am match {
case AbsoluteX | ZeroPageX | IndexedX | AbsoluteIndexedX => false
case _ => true
}
def doesntUseXOrY(am: AddrMode.Value): Boolean = am match {
case Immediate | ZeroPage | Absolute | Relative | Indirect | ZeroPageIndirect => true
case _ => false