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Fixed flag checks during optimisation

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This commit is contained in:
Karol Stasiak 2018-06-04 16:49:45 +02:00
parent c71af26989
commit 10860f6c5f
3 changed files with 15 additions and 15 deletions
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14
src/main/scala/millfork/assembly/opt/AlwaysGoodOptimizations.scala
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@ -664,27 +664,27 @@ object AlwaysGoodOptimizations {
modificationOfJustWrittenValue(STA, AbsoluteX, MatchA(5), DEC, Not(ChangesX), atLeastTwo = false, Seq(), (c, i) => List(
AssemblyLine.immediate(LDA, (c.get[Int](5) - i) & 0xff)
)),
modificationOfJustWrittenValue(STA, Absolute, Anything, INC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, Absolute, HasClear(State.D), INC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(CLC),
AssemblyLine.immediate(ADC, i)
)),
modificationOfJustWrittenValue(STA, Absolute, Anything, DEC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, Absolute, HasClear(State.D), DEC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(SEC),
AssemblyLine.immediate(SBC, i)
)),
modificationOfJustWrittenValue(STA, ZeroPage, Anything, INC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, ZeroPage, HasClear(State.D), INC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(CLC),
AssemblyLine.immediate(ADC, i)
)),
modificationOfJustWrittenValue(STA, ZeroPage, Anything, DEC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, ZeroPage, HasClear(State.D), DEC, Anything, atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(SEC),
AssemblyLine.immediate(SBC, i)
)),
modificationOfJustWrittenValue(STA, AbsoluteX, Anything, INC, Not(ChangesX), atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, AbsoluteX, HasClear(State.D), INC, Not(ChangesX), atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(CLC),
AssemblyLine.immediate(ADC, i)
)),
modificationOfJustWrittenValue(STA, AbsoluteX, Anything, DEC, Not(ChangesX), atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
modificationOfJustWrittenValue(STA, AbsoluteX, HasClear(State.D), DEC, Not(ChangesX), atLeastTwo = true, Seq(State.C, State.V), (_, i) => List(
AssemblyLine.implied(SEC),
AssemblyLine.immediate(SBC, i)
)),
@ -1599,7 +1599,7 @@ object AlwaysGoodOptimizations {
(Elidable & HasOpcode(INC) & MatchAddrMode(0) & MatchParameter(1)) ~~> { code =>
List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))
},
(Elidable & HasOpcode(ASL) & HasAddrMode(AddrMode.Implied)) ~
(Elidable & HasOpcode(ASL) & HasAddrMode(AddrMode.Implied) & HasClear(State.D)) ~
(Elidable & HasOpcode(CLC)) ~
(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { code =>
List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))

4
src/main/scala/millfork/assembly/opt/LaterOptimizations.scala
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@ -301,9 +301,9 @@ object LaterOptimizations {
val cState = if (carrySet) HasSet(State.C) else HasClear(State.C)
val carryOp = if (carrySet) SEC else CLC
(Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes)).capture(11) ~
(Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes) & HasClear(State.D)).capture(11) ~
(Elidable & HasOpcode(carryOp)).? ~
(Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState & HasClear(State.D)) ~
(Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState) ~
(Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) =>
ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) ::
(List.fill(amount)(AssemblyLine.implied(changeOp)) :+

12
src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala
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@ -433,21 +433,21 @@ object UndocumentedOptimizations {
val UseMultiple = new RuleBasedAssemblyOptimization("Using multiple undocumented instructions",
needsFlowInfo = FlowInfoRequirement.BothFlows,
(Elidable & HasOpcode(LDA) & LaxAddrModeRestriction) ~
(Elidable & HasOpcode(LDA) & LaxAddrModeRestriction & HasClear(State.D)) ~
(Elidable & HasOpcode(CLC)).? ~
(Elidable & HasOpcode(ADC) & HasImmediate(2) & HasClear(State.C)) ~
(Elidable & HasOpcode(TAX)) ~~> { (code, ctx) =>
(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
List(code.head.copy(opcode = LAX), AssemblyLine(SBX, Immediate, Constant.Zero - ctx.get[Constant](2)))
},
(Elidable & HasOpcode(LDA) & LaxAddrModeRestriction) ~
(Elidable & HasOpcode(LDA) & LaxAddrModeRestriction & HasClear(State.D)) ~
(Elidable & HasOpcode(SEC)).? ~
(Elidable & HasOpcode(SBC) & HasImmediate(2) & HasSet(State.C)) ~
(Elidable & HasOpcode(TAX)) ~~> { (code, ctx) =>
(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
List(code.head.copy(opcode = LAX), AssemblyLine(SBX, Immediate, ctx.get[Constant](2)))
},
(Elidable & HasOpcode(LDA) & LaxAddrModeRestriction & MatchAddrMode(0) & MatchParameter(1)) ~
(Not(ReadsX) & HasOpcodeIn(Set(ANC, ALR, ARR, ADC, AND, EOR, ORA, ADC, SBC, SEC, CLC, STA, LDY, STY)) |
HasAddrMode(Implied) & HasOpcodeIn(Set(ASL, LSR, ROL, ROR, TAY, TYA))).* ~
(Not(ReadsX) & HasOpcodeIn(Set(ANC, ALR, ARR, ADC, AND, EOR, ORA, ADC, SBC, STA, LDY, STY)) |
HasAddrMode(Implied) & HasOpcodeIn(Set(ASL, LSR, ROL, ROR, TAY, TYA, SEC, CLC, SED, CLD))).* ~
(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~
HasOpcode(LDY).? ~
(Elidable & HasOpcode(AND)) ~