diff --git a/src/main/scala/millfork/Main.scala b/src/main/scala/millfork/Main.scala index 4e58c938..70ccdc59 100644 --- a/src/main/scala/millfork/Main.scala +++ b/src/main/scala/millfork/Main.scala @@ -264,7 +264,7 @@ object Main { val extras = List( if (options.flag(CompilationFlag.EmitIllegals)) UndocumentedOptimizations.All else Nil, if (options.flag(CompilationFlag.Emit65CE02Opcodes)) CE02Optimizations.All else Nil, - if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else LaterOptimizations.Nmos, + if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else NmosOptimizations.All, if (options.flag(CompilationFlag.EmitHudsonOpcodes)) HudsonOptimizations.All else Nil, if (options.flag(CompilationFlag.EmitEmulation65816Opcodes)) SixteenOptimizations.AllForEmulation else Nil, if (options.flag(CompilationFlag.EmitNative65816Opcodes)) SixteenOptimizations.AllForNative else Nil, diff --git a/src/main/scala/millfork/assembly/m6809/opt/VeryLateM6809AssemblyOptimizations.scala b/src/main/scala/millfork/assembly/m6809/opt/VeryLateM6809AssemblyOptimizations.scala index af555b09..60e2e106 100644 --- a/src/main/scala/millfork/assembly/m6809/opt/VeryLateM6809AssemblyOptimizations.scala +++ b/src/main/scala/millfork/assembly/m6809/opt/VeryLateM6809AssemblyOptimizations.scala @@ -10,6 +10,8 @@ import millfork.node.NiceFunctionProperty */ object VeryLateM6809AssemblyOptimizations { + def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[MLine]] = Nil + def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[MLine]] = { val result = Seq.newBuilder[AssemblyOptimization[MLine]] // TODO: add stuff here diff --git a/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala index b3a71d5d..badad500 100644 --- a/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala +++ b/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala @@ -290,54 +290,6 @@ object LaterOptimizations { ) - private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = { - val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes - val stAddrModes = if (useX) StxAddrModes else StyAddrModes - val ldOp = if (useX) LDX else LDY - val stOp = if (useX) STX else STY - val changeOp = if (dec) if (useX) DEX else DEY else if (useX) INX else INY - val addOp = if (dec) SBC else ADC - val addParam = if (dec ^ carrySet) amount + 1 else amount - val indexState = if (useX) State.X else State.Y - val cState = if (carrySet) HasSet(State.C) else HasClear(State.C) - val carryOp = if (carrySet) SEC else CLC - - (Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes) & HasClear(State.D)).capture(11) ~ - (Elidable & HasOpcode(carryOp)).? ~ - (Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState) ~ - (Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) => - ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) :: - (List.fill(amount)(AssemblyLine.implied(changeOp)) :+ - ctx.get[List[AssemblyLine]](12).head.copy(opcode = stOp)) - } - } - - val IncrementThroughIndexRegisters = new RuleBasedAssemblyOptimization("Increment through index registers", - needsFlowInfo = FlowInfoRequirement.BothFlows, - incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = true), - incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = false), - incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = true), - incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = false), - incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = true), - incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = false), - incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = true), - incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = false), - incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = true), - incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = false), - incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = true), - incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = false), - - (Elidable & HasOpcode(TYA) & HasClear(State.D)) ~ - (Elidable & HasOpcode(CLC)) ~ - (Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code => - AssemblyLine.implied(INY).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEY).pos(code(2).source) :: code.drop(3) - }, - (Elidable & HasOpcode(TXA) & HasClear(State.D)) ~ - (Elidable & HasOpcode(CLC)) ~ - (Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code => - AssemblyLine.implied(INX).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEX).pos(code(2).source) :: code.drop(3) - }, - ) val LoadingBranchesOptimization = new RuleBasedAssemblyOptimization("Loading branches optimization", needsFlowInfo = FlowInfoRequirement.BackwardFlow, @@ -451,48 +403,6 @@ object LaterOptimizations { }, ) - val UseIndexedX = new RuleBasedAssemblyOptimization("Using indexed-indirect addressing mode", - needsFlowInfo = FlowInfoRequirement.BothFlows, - - (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ - (Linear & Not(ConcernsY)).* ~ - (Elidable & HasAddrMode(IndexedY) & HasX(0) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { code => - code.tail.init :+ code.last.copy(addrMode = IndexedX) - }, - - (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ - (Linear & Not(ConcernsY)).* ~ - (Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(0xff) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code => - code.tail.init ++ List(AssemblyLine.implied(INX), code.last.copy(addrMode = IndexedX)) - }, - - (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ - (Linear & Not(ConcernsY)).* ~ - (Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(1) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code => - code.tail.init ++ List(AssemblyLine.implied(DEX), code.last.copy(addrMode = IndexedX)) - }, - - (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ - (Linear & Not(ConcernsY)).* ~ - (Elidable & HasAddrMode(IndexedY) & MatchX(1) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx)=> - val lastLine = code.last - code.tail.init ++ List(lastLine.copy(addrMode = IndexedX, parameter = lastLine.parameter - ctx.get[Int](1))) - }, - - (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ - (Linear & Not(ConcernsY)).*.capture(2) ~ - (Elidable & HasAddrMode(IndexedY) & DoesntMatterWhatItDoesWith(State.Y, State.X)).capture(0) ~ - Linear.*.capture(3) ~ - (Elidable & HasOpcode(LDX) & MatchImmediate(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { (code, ctx) => - val mainLine = ctx.get[List[AssemblyLine]](0).head - ctx.get[List[AssemblyLine]](2) ++ List( - code.last, - mainLine.copy(addrMode = IndexedX, parameter = mainLine.parameter - ctx.get[Int](1))) ++ - ctx.get[List[AssemblyLine]](3) - }, - - ) - val UseBit = new RuleBasedAssemblyOptimization("Using BIT instruction", needsFlowInfo = FlowInfoRequirement.BackwardFlow, (Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage))) ~ @@ -648,10 +558,5 @@ object LaterOptimizations { UseXInsteadOfStack, UseYInsteadOfStack, UseZeropageAddressingMode) - - val Nmos = List( - IncrementThroughIndexRegisters, - UseIndexedX - ) } diff --git a/src/main/scala/millfork/assembly/mos/opt/NmosOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/NmosOptimizations.scala new file mode 100644 index 00000000..c7705a6b --- /dev/null +++ b/src/main/scala/millfork/assembly/mos/opt/NmosOptimizations.scala @@ -0,0 +1,116 @@ +package millfork.assembly.mos.opt + +import millfork.assembly._ +import millfork.assembly.mos._ +import millfork.assembly.mos.Opcode._ +import AddrMode._ +import millfork.assembly.mos.OpcodeClasses._ +import millfork.env.{Constant, NormalFunction, NumericConstant} +/** + * @author Karol Stasiak + */ +object NmosOptimizations { + + private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY) + private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX) + private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY) + private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX) + private val StaAddrModes = Set(Absolute, ZeroPage, ZeroPageX, AbsoluteX, IndexedY, IndexedX, AbsoluteY) + private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage) + + private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = { + val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes + val stAddrModes = if (useX) StxAddrModes else StyAddrModes + val ldOp = if (useX) LDX else LDY + val stOp = if (useX) STX else STY + val changeOp = if (dec) if (useX) DEX else DEY else if (useX) INX else INY + val addOp = if (dec) SBC else ADC + val addParam = if (dec ^ carrySet) amount + 1 else amount + val indexState = if (useX) State.X else State.Y + val cState = if (carrySet) HasSet(State.C) else HasClear(State.C) + val carryOp = if (carrySet) SEC else CLC + + (Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes) & HasClear(State.D)).capture(11) ~ + (Elidable & HasOpcode(carryOp)).? ~ + (Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState) ~ + (Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) => + ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) :: + (List.fill(amount)(AssemblyLine.implied(changeOp)) :+ + ctx.get[List[AssemblyLine]](12).head.copy(opcode = stOp)) + } + } + + val IncrementThroughIndexRegisters = new RuleBasedAssemblyOptimization("Increment through index registers", + needsFlowInfo = FlowInfoRequirement.BothFlows, + incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = true), + incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = false), + incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = true), + incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = false), + incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = true), + incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = false), + incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = true), + incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = false), + incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = true), + incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = false), + incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = true), + incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = false), + + (Elidable & HasOpcode(TYA) & HasClear(State.D)) ~ + (Elidable & HasOpcode(CLC)) ~ + (Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code => + AssemblyLine.implied(INY).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEY).pos(code(2).source) :: code.drop(3) + }, + (Elidable & HasOpcode(TXA) & HasClear(State.D)) ~ + (Elidable & HasOpcode(CLC)) ~ + (Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code => + AssemblyLine.implied(INX).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEX).pos(code(2).source) :: code.drop(3) + }, + ) + + val UseIndexedX = new RuleBasedAssemblyOptimization("Using indexed-indirect addressing mode", + needsFlowInfo = FlowInfoRequirement.BothFlows, + + (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ + (Linear & Not(ConcernsY)).* ~ + (Elidable & HasAddrMode(IndexedY) & HasX(0) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { code => + code.tail.init :+ code.last.copy(addrMode = IndexedX) + }, + + (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ + (Linear & Not(ConcernsY)).* ~ + (Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(0xff) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code => + code.tail.init ++ List(AssemblyLine.implied(INX), code.last.copy(addrMode = IndexedX)) + }, + + (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ + (Linear & Not(ConcernsY)).* ~ + (Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(1) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code => + code.tail.init ++ List(AssemblyLine.implied(DEX), code.last.copy(addrMode = IndexedX)) + }, + + (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ + (Linear & Not(ConcernsY)).* ~ + (Elidable & HasAddrMode(IndexedY) & MatchX(1) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx)=> + val lastLine = code.last + code.tail.init ++ List(lastLine.copy(addrMode = IndexedX, parameter = lastLine.parameter - ctx.get[Int](1))) + }, + + (Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~ + (Linear & Not(ConcernsY)).*.capture(2) ~ + (Elidable & HasAddrMode(IndexedY) & DoesntMatterWhatItDoesWith(State.Y, State.X)).capture(0) ~ + Linear.*.capture(3) ~ + (Elidable & HasOpcode(LDX) & MatchImmediate(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { (code, ctx) => + val mainLine = ctx.get[List[AssemblyLine]](0).head + ctx.get[List[AssemblyLine]](2) ++ List( + code.last, + mainLine.copy(addrMode = IndexedX, parameter = mainLine.parameter - ctx.get[Int](1))) ++ + ctx.get[List[AssemblyLine]](3) + }, + + ) + + val All: List[AssemblyOptimization[AssemblyLine]] = List( + IncrementThroughIndexRegisters, + UseIndexedX + ) +} diff --git a/src/main/scala/millfork/assembly/mos/opt/SuperOptimizer.scala b/src/main/scala/millfork/assembly/mos/opt/SuperOptimizer.scala index ec16d7a3..6c166813 100644 --- a/src/main/scala/millfork/assembly/mos/opt/SuperOptimizer.scala +++ b/src/main/scala/millfork/assembly/mos/opt/SuperOptimizer.scala @@ -24,7 +24,7 @@ object SuperOptimizer extends AssemblyOptimization[AssemblyLine] { if (options.flag(CompilationFlag.EmitCmosOpcodes)) { allOptimizers ++= CmosOptimizations.All } else { - allOptimizers ++= LaterOptimizations.Nmos + allOptimizers ++= NmosOptimizations.All } if (options.flag(CompilationFlag.EmitEmulation65816Opcodes)) { allOptimizers ++= SixteenOptimizations.AllForEmulation diff --git a/src/main/scala/millfork/assembly/mos/opt/VeryLateMosAssemblyOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/VeryLateMosAssemblyOptimizations.scala index 8162a2d8..ee278551 100644 --- a/src/main/scala/millfork/assembly/mos/opt/VeryLateMosAssemblyOptimizations.scala +++ b/src/main/scala/millfork/assembly/mos/opt/VeryLateMosAssemblyOptimizations.scala @@ -14,7 +14,7 @@ import millfork.assembly.mos.AddrMode._ //noinspection ZeroIndexToHead object VeryLateMosAssemblyOptimizations { - val StoresOfImmediatesDifferingByOneViaX = new RuleBasedAssemblyOptimization("", + val StoresOfImmediatesDifferingByOneViaX = new RuleBasedAssemblyOptimization("Use X to store immediates differing by 1", needsFlowInfo = FlowInfoRequirement.BothFlows, (Elidable & HasOpcode(LDA) & HasAddrMode(Immediate) & MatchNumericImmediate(0) & HasIndex8) ~ (Elidable & HasOpcode(STA) & HasAddrModeIn(ZeroPage, Absolute) & DoesntMatterWhatItDoesWith(State.A, State.X)) ~ @@ -30,7 +30,7 @@ object VeryLateMosAssemblyOptimizations { } ) - val StoresOfImmediatesDifferingByOneViaY = new RuleBasedAssemblyOptimization("", + val StoresOfImmediatesDifferingByOneViaY = new RuleBasedAssemblyOptimization("Use Y to store immediates differing by 1", needsFlowInfo = FlowInfoRequirement.BothFlows, (Elidable & HasOpcode(LDA) & HasAddrMode(Immediate) & MatchNumericImmediate(0) & HasIndex8) ~ (Elidable & HasOpcode(STA) & HasAddrModeIn(ZeroPage, Absolute) & DoesntMatterWhatItDoesWith(State.A, State.Y)) ~ @@ -46,6 +46,8 @@ object VeryLateMosAssemblyOptimizations { } ) + def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[AssemblyLine]] = Nil + def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[AssemblyLine]] = { val result = Seq.newBuilder[AssemblyOptimization[AssemblyLine]] if (!nice(MosNiceFunctionProperty.DoesntChangeX)){ diff --git a/src/main/scala/millfork/assembly/z80/opt/VeryLateI80AssemblyOptimizations.scala b/src/main/scala/millfork/assembly/z80/opt/VeryLateI80AssemblyOptimizations.scala index c11e635f..7ad5339b 100644 --- a/src/main/scala/millfork/assembly/z80/opt/VeryLateI80AssemblyOptimizations.scala +++ b/src/main/scala/millfork/assembly/z80/opt/VeryLateI80AssemblyOptimizations.scala @@ -10,6 +10,8 @@ import millfork.node.NiceFunctionProperty */ object VeryLateI80AssemblyOptimizations { + def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[ZLine]] = Nil + def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[ZLine]] = { val result = Seq.newBuilder[AssemblyOptimization[ZLine]] // TODO: add stuff here diff --git a/src/test/scala/millfork/test/emu/EmuOptimizedInlinedRun.scala b/src/test/scala/millfork/test/emu/EmuOptimizedInlinedRun.scala index 570919f5..0145e341 100644 --- a/src/test/scala/millfork/test/emu/EmuOptimizedInlinedRun.scala +++ b/src/test/scala/millfork/test/emu/EmuOptimizedInlinedRun.scala @@ -1,7 +1,7 @@ package millfork.test.emu import millfork.assembly.m6809.opt.M6809OptimizationPresets -import millfork.assembly.mos.opt.{LaterOptimizations, ZeropageRegisterOptimizations} +import millfork.assembly.mos.opt.{LaterOptimizations, NmosOptimizations, ZeropageRegisterOptimizations} import millfork.assembly.z80.opt.Z80OptimizationPresets import millfork.{Cpu, OptimizationPresets} @@ -16,10 +16,10 @@ object EmuOptimizedInlinedRun extends EmuRun( OptimizationPresets.Good ++ OptimizationPresets.Good ++ OptimizationPresets.AssOpt ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ ZeropageRegisterOptimizations.All ++ OptimizationPresets.AssOpt ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ ZeropageRegisterOptimizations.All ++ OptimizationPresets.AssOpt ++ OptimizationPresets.AssOpt ++ diff --git a/src/test/scala/millfork/test/emu/EmuOptimizedRun.scala b/src/test/scala/millfork/test/emu/EmuOptimizedRun.scala index 61b0baf4..1c772961 100644 --- a/src/test/scala/millfork/test/emu/EmuOptimizedRun.scala +++ b/src/test/scala/millfork/test/emu/EmuOptimizedRun.scala @@ -1,7 +1,7 @@ package millfork.test.emu import millfork.assembly.m6809.opt.M6809OptimizationPresets -import millfork.assembly.mos.opt.{LaterOptimizations, ZeropageRegisterOptimizations} +import millfork.assembly.mos.opt.{LaterOptimizations, NmosOptimizations, ZeropageRegisterOptimizations} import millfork.assembly.z80.opt.{AlwaysGoodZ80Optimizations, Z80OptimizationPresets} import millfork.{Cpu, OptimizationPresets} @@ -15,8 +15,8 @@ object EmuOptimizedRun extends EmuRun( ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ ZeropageRegisterOptimizations.All ++ @@ -47,8 +47,8 @@ object EmuSizeOptimizedRun extends EmuRun( ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ ZeropageRegisterOptimizations.All ++ @@ -66,8 +66,8 @@ object EmuOptimizedSoftwareStackRun extends EmuRun( ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ ZeropageRegisterOptimizations.All ++ OptimizationPresets.Good ++ ZeropageRegisterOptimizations.All ++ diff --git a/src/test/scala/millfork/test/emu/EmuRun.scala b/src/test/scala/millfork/test/emu/EmuRun.scala index 8b98d9e8..afecdc96 100644 --- a/src/test/scala/millfork/test/emu/EmuRun.scala +++ b/src/test/scala/millfork/test/emu/EmuRun.scala @@ -222,7 +222,7 @@ class EmuRun(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimization], val env2 = new Environment(None, "", CpuFamily.M6502, options) env2.collectDeclarations(program, options) val assembler = new MosAssembler(program, env2, platform) - val output = assembler.assemble(callGraph, assemblyOptimizations, options, VeryLateMosAssemblyOptimizations.All) + val output = assembler.assemble(callGraph, assemblyOptimizations, options, if (assemblyOptimizations.nonEmpty) VeryLateMosAssemblyOptimizations.All else VeryLateMosAssemblyOptimizations.None) println(";;; compiled: -----------------") output.asm.takeWhile(s => !(s.startsWith(".") && s.contains("= $"))).filterNot(_.contains("; DISCARD_")).foreach(println) println(";;; ---------------------------") diff --git a/src/test/scala/millfork/test/emu/EmuUndocumentedRun.scala b/src/test/scala/millfork/test/emu/EmuUndocumentedRun.scala index 5f8ba7da..86a30d82 100644 --- a/src/test/scala/millfork/test/emu/EmuUndocumentedRun.scala +++ b/src/test/scala/millfork/test/emu/EmuUndocumentedRun.scala @@ -1,6 +1,6 @@ package millfork.test.emu -import millfork.assembly.mos.opt.{LaterOptimizations, UndocumentedOptimizations} +import millfork.assembly.mos.opt.{NmosOptimizations, UndocumentedOptimizations} import millfork.{Cpu, OptimizationPresets} /** @@ -9,13 +9,13 @@ import millfork.{Cpu, OptimizationPresets} object EmuUndocumentedRun extends EmuRun( Cpu.Ricoh, // not Cpu.Mos, because I haven't found an emulator that supports both illegals and decimal mode yet OptimizationPresets.NodeOpt, - OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++ + OptimizationPresets.AssOpt ++ NmosOptimizations.All ++ UndocumentedOptimizations.All ++ - OptimizationPresets.Good ++ LaterOptimizations.Nmos ++ + OptimizationPresets.Good ++ NmosOptimizations.All ++ UndocumentedOptimizations.All ++ - OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++ + OptimizationPresets.AssOpt ++ NmosOptimizations.All ++ UndocumentedOptimizations.All ++ - OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++ + OptimizationPresets.AssOpt ++ NmosOptimizations.All ++ UndocumentedOptimizations.All ++ OptimizationPresets.Good) {